ram_basic.msg

《设计与验证Verilog HDL》光盘内容

@TM:1136910347
@N: FX164 :"":0:0:0:-1|The option to pack flops in the IOB has not been specified 
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1136910344
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@N:  :"c:\prj\example-4-6\ram_basic\ram_basic.v":1:7:1:15|Synthesizing module ram_basic
@TM:1136910816
@N: CL134 :"c:\prj\example-4-6\ram_basic\ram_basic.v":13:5:13:10|M