bibus.tlg

来自「《设计与验证Verilog HDL》光盘内容」· TLG 代码 · 共 6 行

Selecting top level module bibus
@N:"C:\prj\Example-5-1\bibus\decode.v":1:7:1:12|Synthesizing module decode

@N:"C:\prj\Example-5-1\bibus\bibus.v":1:7:1:11|Synthesizing module bibus