_primary.vhd

来自「《设计与验证Verilog HDL》光盘内容」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity clock_edge is
    port(
        clk_50m         : in     vl_logic;
        clk_100m        : in     vl_logic;
        \rst_\          : in     vl_logic;
        cnt1            : out    vl_logic_vector(3 downto 0);
        cnt2            : out    vl_logic_vector(3 downto 0)
    );
end clock_edge;