clock_edge.msg

来自「《设计与验证Verilog HDL》光盘内容」· MSG 代码 · 共 6 行

@TM:1136828624
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1136828621
@N:  :"c:\prj\example-4-2\clock_edge.v":1:7:1:16|Synthesizing module clock_edge