latch_mult_if.msg

来自「《设计与验证Verilog HDL》光盘内容」· MSG 代码 · 共 7 行

@TM:1137578399
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@TM:1137578395
@N:  :"c:\prj\example-4-10\if_mult\latch_if_mult\latch_mult_if.v":1:7:1:13|Synthesizing module mult_if