if_mult_decode.prd

来自「《设计与验证Verilog HDL》光盘内容」· PRD 代码 · 共 14 行

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file C:\prj\Example-4-10\decode\if_mult\if_mult_decode.prd
#-- Written on Mon Jan 16 09:32:53 2006

#
### Watch Implementation type ###
#
watch_impl -all
#
### Watch Implementation properties ###
#
watch_prop -clear