_info

来自「《设计与验证Verilog HDL》光盘内容」· 代码 · 共 26 行

m255
cModel Technology
dC:\Modeltech_5.8b\examples
vclk_3div
Iggk;a5VlBMMaJll8e]GHJ2
V=njA=jHBl<1bm@b482W]g2
dC:\prj\Example-4-14\clk_3div\sim
w1141827240
FC:/prj/Example-4-14/clk_3div/clk_3div.v
L0 1
OE;L;5.8b;17
r1
31
o-work work
vclk_3div_tb
IV0`DKj:0TK3z^RfIHaN=B1
VN`kd85llAAfMjDC542P^N0
dC:\prj\Example-4-14\clk_3div\sim
w1141827261
FC:/prj/Example-4-14/clk_3div/clk_3div_tb.v
L0 2
OE;L;5.8b;17
r1
31
o-work work