clk_div3.prj

来自「《设计与验证Verilog HDL》光盘内容」· PRJ 代码 · 共 49 行

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file C:\prj\Example-4-14\clk_3div\synthesis\clk_div3.prj
#-- Written on Wed Mar 08 22:24:43 2006


#add_file options
add_file -verilog "C:/prj/Example-4-14/clk_3div/clk_3div.v"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology ISPMACH4000V
set_option -part LC4064V
set_option -package T100C
set_option -speed_grade -2.5

#compilation/mapping options
set_option -default_enum_encoding sequential
set_option -symbolic_fsm_compiler 0
set_option -resource_sharing 0

#map options
set_option -frequency 1.000
set_option -fanin_limit 20
set_option -max_terms_per_macrocell 16
set_option -domap 0
set_option -area_delay_percent 0
set_option -disable_io_insertion 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/clk_3div.edf"

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1
impl -active "rev_1"