clk_3div.srr

来自「《设计与验证Verilog HDL》光盘内容」· SRR 代码 · 共 38 行

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Wed Mar 08 22:24:43 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\prj\Example-4-14\clk_3div\clk_3div.v"
Verilog syntax check successful!
Selecting top level module clk_3div
@N:"C:\prj\Example-4-14\clk_3div\clk_3div.v":1:7:1:14|Synthesizing module clk_3div

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Mar 08 22:24:43 2006

###########################################################[
Version 8.1
Synplicity CPLD Technology Mapper, Version 8.1.0, Build 532R, Built Apr 28 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
---------------------------------------
Resource Usage Report

Simple gate primitives:
DFFRH           3 uses
IBUF            2 uses
OBUF            1 use
INV             3 uses
AND2            2 uses


@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################]