_primary.vhd

来自「《设计与验证Verilog HDL》光盘内容」· VHDL 代码 · 共 8 行

library verilog;
use verilog.vl_types.all;
entity clk_div_phase_tb is
    generic(
        period          : integer := 5
    );
end clk_div_phase_tb;