_primary.vhd

来自「《设计与验证Verilog HDL》光盘内容」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity clk_div_phase is
    port(
        rst             : in     vl_logic;
        clk_200m        : in     vl_logic;
        clk_100m        : out    vl_logic;
        clk_50m         : out    vl_logic;
        clk_25m         : out    vl_logic
    );
end clk_div_phase;