state2_default.prf

《设计与验证Verilog HDL》光盘内容

#
# Logical Preferences generated for Lucent by Synplify 8.1.0, Build 532R.
#

# Period Constraints
FREQUENCY PORT "clk" 364.2 MHz;
# Output Constraints
# Input Constraints

BLOCK ASYNCPATHS;

# End of generated Logical Preferences.