state1.prf

来自「《设计与验证Verilog HDL》光盘内容」· PRF 代码 · 共 13 行

#
# Logical Preferences generated for Lucent by Synplify 8.1.0, Build 532R.
#

# Period Constraints
FREQUENCY PORT "clk" 509.9 MHz;
# Output Constraints
# Input Constraints

BLOCK ASYNCPATHS;

# End of generated Logical Preferences.