cs.txt

《设计与验证Verilog HDL》光盘内容

indata[0] = 3'b100 ; outdata[0] = 4'b0001; 
indata[1] = 3'b000 ; outdata[1] = 4'b0001; 
indata[2] = 3'b111 ; outdata[2] = 4'b0001; 
indata[3] = 3'b011 ; outdata[3] = 4'b0010; 
indata[4] = 3'b000 ; outdata[4] = 4'b0010; 
indata[5] = 3'b111 ; outdata[5] = 4'b0001; 
indata[6] = 3'b011 ; outdata[6] = 4'b0010; 
indata[7] = 3'b011 ; outdata[7] = 4'b0100; 
indata[8] = 3'b001 ; outdata[8] = 4'b0001; 
indata[9] = 3'b111 ; outdata[9] = 4'b0001; 
indata[10] = 3'b011 ; outdata[10] = 4'b0010; 
indata[11] = 3'b011 ; outdata[11] = 4'b0100; 
indata[12] = 3'b010 ; outdata[12] = 4'b0100; 
indata[13] = 3'b111 ; outdata[13] = 4'b0001; 
indata[14] = 3'b011 ; outdata[14] = 4'b0010; 
indata[15] = 3'b011 ; outdata[15] = 4'b0100; 
indata[16] = 3'b000 ; outdata[16] = 4'b1000; 
indata[17] = 3'b000 ; outdata[17] = 4'b0001; 
indata[18] = 3'b111 ; outdata[18] = 4'b0001; 
indata[19] = 3'b011 ; outdata[19] = 4'b0010; 
indata[20] = 3'b011 ; outdata[20] = 4'b0100; 
indata[21] = 3'b000 ; outdata[21] = 4'b1000; 
indata[22] = 3'b001 ; outdata[22] = 4'b1000; 
indata[23] = 3'b111 ; outdata[23] = 4'b0001; 
indata[24] = 3'b011 ; outdata[24] = 4'b0010; 
indata[25] = 3'b010 ; outdata[25] = 4'b1000; 
indata[26] = 3'b101 ; outdata[26] = 4'b0001; 
indata[27] = 3'b001 ; outdata[27] = 4'b1000;