state2.msg

《设计与验证Verilog HDL》光盘内容

@TM:1134714704
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@N:  :"c:\prj\fsm_abc\state2\state2.v":7:7:7:12|Synthesizing module state2
@N: CL201 :"c:\prj\fsm_abc\state2\state2.v":28:0:28:5|M