state2.prd

《设计与验证Verilog HDL》光盘内容

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file C:\prj\Example-6-1\FSM\state2\state2.prd
#-- Written on Fri Dec 16 18:27:33 2005

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### Watch Implementation type ###
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watch_impl -all
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### Watch Implementation properties ###
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watch_prop -clear {  state2|clk - Estimated Frequency }