📄 mealy.rpt
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& = Uses single-pin Output Enable
Device-Specific Information: c:\mealy2\mealy.rpt
mealy
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 16 DFFE + 1 1 0 1 state~1
- 4 - B 16 DFFE + 1 1 0 3 state~2
- 5 - B 16 DFFE + 1 1 0 5 state~3
- 6 - B 16 DFFE + 1 1 0 5 state~4
- 1 - B 16 OR2 s 1 3 1 0 ~376~1
- 7 - B 16 OR2 1 2 1 0 :390
- 8 - B 16 AND2 1 2 1 0 :402
- 3 - B 16 OR2 s 1 3 1 0 ~412~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\mealy2\mealy.rpt
mealy
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\mealy2\mealy.rpt
mealy
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: c:\mealy2\mealy.rpt
mealy
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 rst
Device-Specific Information: c:\mealy2\mealy.rpt
mealy
** EQUATIONS **
clk : INPUT;
in1 : INPUT;
rst : INPUT;
-- Node name is 'out10'
-- Equation name is 'out10', type is output
out10 = _LC3_B16;
-- Node name is 'out11'
-- Equation name is 'out11', type is output
out11 = _LC8_B16;
-- Node name is 'out12'
-- Equation name is 'out12', type is output
out12 = _LC7_B16;
-- Node name is 'out13'
-- Equation name is 'out13', type is output
out13 = _LC1_B16;
-- Node name is 'state~1'
-- Equation name is 'state~1', location is LC2_B16, type is buried.
state~1 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ001 = in1 & state~2
# in1 & state~1;
-- Node name is 'state~2'
-- Equation name is 'state~2', location is LC4_B16, type is buried.
state~2 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ002 = !in1 & state~3
# !in1 & state~2;
-- Node name is 'state~3'
-- Equation name is 'state~3', location is LC5_B16, type is buried.
state~3 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ003 = in1 & !state~4
# in1 & state~3;
-- Node name is 'state~4'
-- Equation name is 'state~4', location is LC6_B16, type is buried.
state~4 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!rst), VCC, VCC);
_EQ004 = !state~1 & state~4
# in1;
-- Node name is '~376~1'
-- Equation name is '~376~1', location is LC1_B16, type is buried.
-- synthesized logic cell
_LC1_B16 = LCELL( _EQ005);
_EQ005 = state~2 & state~4
# state~3 & state~4
# in1;
-- Node name is ':390'
-- Equation name is '_LC7_B16', type is buried
_LC7_B16 = LCELL( _EQ006);
_EQ006 = !in1 & state~3 & state~4
# in1 & !state~3 & state~4;
-- Node name is ':402'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = LCELL( _EQ007);
_EQ007 = in1 & !state~3 & state~4;
-- Node name is '~412~1'
-- Equation name is '~412~1', location is LC3_B16, type is buried.
-- synthesized logic cell
_LC3_B16 = LCELL( _EQ008);
_EQ008 = in1
# state~2 & !state~3 & state~4;
Project Information c:\mealy2\mealy.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,509K
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