mealy.vhd

来自「MEALY状态机的输出是现态和输入的函数.在SRAM控制器状态机中,写有效WE不」· VHDL 代码 · 共 67 行

library ieee;
use ieee.std_logic_1164.all;
entity mealy is
	port( clk,in1,rst:	in	std_logic;
		out1:	out	std_logic_vector(3 downto 0));
end;
architecture a of mealy is
type state_type is (s0,s1,s2,s3);
signal state:state_type;
begin
	mealy_process:process(clk,rst)
	begin
		if rst='1' then
			state<=s0;
		elsif rising_edge(clk) then
			case state is 
				when s0 =>
                          if in1='1' then
						     state<=s1;
					      end if;
				when s1 =>
                          if in1='0' then
						     state<=s2;
					      end if;
				when s2 =>
                          if in1='1' then
						     state<=s3;
					      end if;
				when s3 =>
                          if in1='0' then
						     state<=s0;
					      end if;
				end case;
			end if;
	end process mealy_process;
	output_process:process(state,in1)
	begin
		case state is
			when s0 =>
				if in1='1' then
					out1<="1001";
				else 
					out1<="0000";
				end if;
			when s1 =>
				if in1='0' then
					out1<="1100";
				else 
					out1<="1001";
				end if;
			when s2 =>
				if in1='1' then
					out1<="1111";
				else 
					out1<="1001";
				end if;
			when s3 =>
				if in1='0' then
					out1<="0000";
				else 
					out1<="1111";
				end if;
		end case;
	end process output_process;
end a;