📄 clk_div5_vhd.sdo
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// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP1C3T144C8 Package TQFP144
//
//
// This SDF file should be used for ModelSim (VHDL) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "clk_div5")
(DATE "05/28/2007 16:37:44")
(VENDOR "Altera")
(PROGRAM "Quartus II")
(VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cyclone_asynch_io")
(INSTANCE \\clk\~I\\.asynch_inst)
(DELAY
(ABSOLUTE
(IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
)
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\countr\[1\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (565:565:565) (564:564:564))
(PORT datac (597:597:597) (605:605:605))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datac regin (478:478:478) (478:478:478))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\countr\[1\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (1261:1261:1261) (1241:1241:1241))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\countr\[2\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (568:568:568) (567:567:567))
(PORT datac (591:591:591) (597:597:597))
(PORT datad (564:564:564) (554:554:554))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datac regin (478:478:478) (478:478:478))
(IOPATH datad regin (309:309:309) (309:309:309))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\countr\[2\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (1261:1261:1261) (1241:1241:1241))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\countr\[0\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (568:568:568) (566:566:566))
(PORT datac (591:591:591) (599:599:599))
(PORT datad (566:566:566) (556:556:556))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datac regin (478:478:478) (478:478:478))
(IOPATH datad regin (309:309:309) (309:309:309))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\countr\[0\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (1261:1261:1261) (1241:1241:1241))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\levelr\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (600:600:600) (590:590:590))
(PORT datab (565:565:565) (561:561:561))
(PORT datac (574:574:574) (587:587:587))
(PORT datad (571:571:571) (561:561:561))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datac regin (478:478:478) (478:478:478))
(IOPATH datad regin (309:309:309) (309:309:309))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\levelr\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (1261:1261:1261) (1241:1241:1241))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\countf\[1\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (565:565:565) (564:564:564))
(PORT datac (594:594:594) (603:603:603))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datac regin (478:478:478) (478:478:478))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\countf\[1\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (1241:1241:1241) (1261:1261:1261))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\countf\[0\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (566:566:566) (564:564:564))
(PORT datac (594:594:594) (603:603:603))
(PORT datad (567:567:567) (557:557:557))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datac regin (478:478:478) (478:478:478))
(IOPATH datad regin (309:309:309) (309:309:309))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\countf\[0\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (1241:1241:1241) (1261:1261:1261))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\countf\[2\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (567:567:567) (566:566:566))
(PORT datac (594:594:594) (603:603:603))
(PORT datad (560:560:560) (551:551:551))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datac regin (478:478:478) (478:478:478))
(IOPATH datad regin (309:309:309) (309:309:309))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\countf\[2\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (1241:1241:1241) (1261:1261:1261))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\levelf\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (572:572:572) (567:567:567))
(PORT datab (565:565:565) (563:563:563))
(PORT datac (594:594:594) (603:603:603))
(PORT datad (524:524:524) (529:529:529))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datac regin (478:478:478) (478:478:478))
(IOPATH datad regin (309:309:309) (309:309:309))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\levelf\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (1241:1241:1241) (1261:1261:1261))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\clk_div\~0_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datac (575:575:575) (587:587:587))
(PORT datad (528:528:528) (531:531:531))
(IOPATH datac combout (292:292:292) (292:292:292))
(IOPATH datad combout (114:114:114) (114:114:114))
)
)
)
(CELL
(CELLTYPE "cyclone_asynch_io")
(INSTANCE \\clk_div\~I\\.asynch_inst)
(DELAY
(ABSOLUTE
(PORT datain (816:816:816) (1093:1093:1093))
(IOPATH datain padio (2124:2124:2124) (2124:2124:2124))
)
)
)
)
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