clk_div5.vho

对任意始终进行精确的5分频处理,而且没有毛刺,效果很好.

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "05/28/2007 16:37:44"

-- 
-- Device: Altera EP1C3T144C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cyclone;
USE IEEE.std_logic_1164.all;
USE cyclone.cyclone_components.all;

ENTITY 	clk_div5 IS
    PORT (
	clk : IN std_logic;
	clk_div : OUT std_logic
	);
END clk_div5;

ARCHITECTURE structure OF clk_div5 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_clk_div : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \countr[1]\ : std_logic;
SIGNAL \countr[2]\ : std_logic;
SIGNAL \countr[0]\ : std_logic;
SIGNAL levelr : std_logic;
SIGNAL \countf[1]\ : std_logic;
SIGNAL \countf[0]\ : std_logic;
SIGNAL \countf[2]\ : std_logic;
SIGNAL levelf : std_logic;
SIGNAL \clk_div~0\ : std_logic;
SIGNAL \ALT_INV_clk~combout\ : std_logic;

BEGIN

ww_clk <= clk;
clk_div <= ww_clk_div;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_clk~combout\ <= NOT \clk~combout\;

\clk~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => \clk~combout\);

\countr[1]~I\ : cyclone_lcell
-- Equation(s):
-- \countr[1]\ = DFFEAS(\countr[1]\ $ \countr[0]\, GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "3C3C",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datab => \countr[1]\,
	datac => \countr[0]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \countr[1]\);

\countr[2]~I\ : cyclone_lcell
-- Equation(s):
-- \countr[2]\ = DFFEAS(\countr[1]\ & (\countr[0]\ $ \countr[2]\) # !\countr[1]\ & \countr[0]\ & \countr[2]\, GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "3CC0",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datab => \countr[1]\,
	datac => \countr[0]\,
	datad => \countr[2]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \countr[2]\);

\countr[0]~I\ : cyclone_lcell
-- Equation(s):
-- \countr[0]\ = DFFEAS(!\countr[0]\ & (\countr[1]\ # !\countr[2]\), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0C0F",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datab => \countr[1]\,
	datac => \countr[0]\,
	datad => \countr[2]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \countr[0]\);

\levelr~I\ : cyclone_lcell
-- Equation(s):
-- levelr = DFFEAS(\countr[0]\ & (levelr) # !\countr[0]\ & (\countr[2]\ & (levelr) # !\countr[2]\ & !\countr[1]\), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F0B1",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => \countr[0]\,
	datab => \countr[1]\,
	datac => levelr,
	datad => \countr[2]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => levelr);

\countf[1]~I\ : cyclone_lcell
-- Equation(s):
-- \countf[1]\ = DFFEAS(\countf[0]\ $ \countf[1]\, !GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "3C3C",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datab => \countf[0]\,
	datac => \countf[1]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \countf[1]\);

\countf[0]~I\ : cyclone_lcell
-- Equation(s):
-- \countf[0]\ = DFFEAS(!\countf[0]\ & (\countf[1]\ # !\countf[2]\), !GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "3033",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datab => \countf[0]\,
	datac => \countf[1]\,
	datad => \countf[2]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \countf[0]\);

\countf[2]~I\ : cyclone_lcell
-- Equation(s):
-- \countf[2]\ = DFFEAS(\countf[0]\ & (\countf[1]\ $ \countf[2]\) # !\countf[0]\ & \countf[1]\ & \countf[2]\, !GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "3CC0",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datab => \countf[0]\,
	datac => \countf[1]\,
	datad => \countf[2]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \countf[2]\);

\levelf~I\ : cyclone_lcell
-- Equation(s):
-- levelf = DFFEAS(\countf[2]\ & (levelf) # !\countf[2]\ & (\countf[0]\ & (levelf) # !\countf[0]\ & !\countf[1]\), !GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "EF01",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	dataa => \countf[2]\,
	datab => \countf[0]\,
	datac => \countf[1]\,
	datad => levelf,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => levelf);

\clk_div~0_I\ : cyclone_lcell
-- Equation(s):
-- \clk_div~0\ = levelr # levelf

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => levelr,
	datad => levelf,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \clk_div~0\);

\clk_div~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \clk_div~0\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_clk_div);
END structure;