lift.tan.qmsg

用fpga控制电梯,实现五层电梯的升降控制,运用vhdl编辑程序.

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "st_ch register ladd\[0\] register ladd\[0\] 108.11 MHz 9.25 ns Internal " "Info: Clock \"st_ch\" has Internal fmax of 108.11 MHz between source register \"ladd\[0\]\" and destination register \"ladd\[0\]\" (period= 9.25 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.733 ns + Longest register register " "Info: + Longest register to register delay is 4.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ladd\[0\] 1 REG LC_X12_Y12_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y12_N5; Fanout = 4; REG Node = 'ladd\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { ladd[0] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.368 ns) + CELL(0.075 ns) 2.443 ns Mux~727 2 COMB LC_X13_Y14_N1 1 " "Info: 2: + IC(2.368 ns) + CELL(0.075 ns) = 2.443 ns; Loc. = LC_X13_Y14_N1; Fanout = 1; COMB Node = 'Mux~727'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "2.443 ns" { ladd[0] Mux~727 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.183 ns) 2.966 ns Mux~729 3 COMB LC_X13_Y14_N2 1 " "Info: 3: + IC(0.340 ns) + CELL(0.183 ns) = 2.966 ns; Loc. = LC_X13_Y14_N2; Fanout = 1; COMB Node = 'Mux~729'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.523 ns" { Mux~727 Mux~729 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.977 ns) + CELL(0.075 ns) 4.018 ns Mux~731 4 COMB LC_X12_Y12_N2 1 " "Info: 4: + IC(0.977 ns) + CELL(0.075 ns) = 4.018 ns; Loc. = LC_X12_Y12_N2; Fanout = 1; COMB Node = 'Mux~731'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.052 ns" { Mux~729 Mux~731 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.366 ns) 4.733 ns ladd\[0\] 5 REG LC_X12_Y12_N5 4 " "Info: 5: + IC(0.349 ns) + CELL(0.366 ns) = 4.733 ns; Loc. = LC_X12_Y12_N5; Fanout = 4; REG Node = 'ladd\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.715 ns" { Mux~731 ladd[0] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.699 ns ( 14.77 % ) " "Info: Total cell delay = 0.699 ns ( 14.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.034 ns ( 85.23 % ) " "Info: Total interconnect delay = 4.034 ns ( 85.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "4.733 ns" { ladd[0] Mux~727 Mux~729 Mux~731 ladd[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.733 ns" { ladd[0] Mux~727 Mux~729 Mux~731 ladd[0] } { 0.000ns 2.368ns 0.340ns 0.977ns 0.349ns } { 0.000ns 0.075ns 0.183ns 0.075ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.928 ns - Smallest " "Info: - Smallest clock skew is -3.928 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "st_ch destination 7.428 ns + Shortest register " "Info: + Shortest clock path from clock \"st_ch\" to destination register is 7.428 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns st_ch 1 CLK PIN_M21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 3; CLK Node = 'st_ch'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { st_ch } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.280 ns) 2.387 ns p2~2635 2 COMB LC_X13_Y14_N6 4 " "Info: 2: + IC(1.382 ns) + CELL(0.280 ns) = 2.387 ns; Loc. = LC_X13_Y14_N6; Fanout = 4; COMB Node = 'p2~2635'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.662 ns" { st_ch p2~2635 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.504 ns) + CELL(0.280 ns) 3.171 ns p2~2646 3 COMB LC_X14_Y14_N8 3 " "Info: 3: + IC(0.504 ns) + CELL(0.280 ns) = 3.171 ns; Loc. = LC_X14_Y14_N8; Fanout = 3; COMB Node = 'p2~2646'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.784 ns" { p2~2635 p2~2646 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.075 ns) 3.572 ns p2~2652 4 COMB LC_X14_Y14_N0 1 " "Info: 4: + IC(0.326 ns) + CELL(0.075 ns) = 3.572 ns; Loc. = LC_X14_Y14_N0; Fanout = 1; COMB Node = 'p2~2652'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.401 ns" { p2~2646 p2~2652 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.786 ns) + CELL(0.075 ns) 4.433 ns ur\[1\] 5 REG LC_X12_Y14_N6 3 " "Info: 5: + IC(0.786 ns) + CELL(0.075 ns) = 4.433 ns; Loc. = LC_X12_Y14_N6; Fanout = 3; REG Node = 'ur\[1\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.861 ns" { p2~2652 ur[1] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }