lift.tan.qmsg

来自「用fpga控制电梯,实现五层电梯的升降控制,运用vhdl编辑程序.」· QMSG 代码 · 共 9 行 · 第 1/5 页

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off lift -c lift --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lift -c lift --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "ladd\[1\] " "Warning: Node \"ladd\[1\]\" is a latch" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ur\[4\] " "Warning: Node \"ur\[4\]\" is a latch" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ur\[2\] " "Warning: Node \"ur\[2\]\" is a latch" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ur\[3\] " "Warning: Node \"ur\[3\]\" is a latch" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ur\[1\] " "Warning: Node \"ur\[1\]\" is a latch" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ur\[6\] " "Warning: Node \"ur\[6\]\" is a latch" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ur\[5\] " "Warning: Node \"ur\[5\]\" is a latch" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ladd\[0\] " "Warning: Node \"ladd\[0\]\" is a latch" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}