lift.tan.qmsg

用fpga控制电梯,实现五层电梯的升降控制,运用vhdl编辑程序.

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register ladd\[1\] register wai_t\[0\] 39.7 MHz 25.192 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 39.7 MHz between source register \"ladd\[1\]\" and destination register \"wai_t\[0\]\" (period= 25.192 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.479 ns + Longest register register " "Info: + Longest register to register delay is 2.479 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ladd\[1\] 1 REG LC_X12_Y12_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y12_N1; Fanout = 6; REG Node = 'ladd\[1\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { ladd[1] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.548 ns) + CELL(0.366 ns) 0.914 ns wai_t~174 2 COMB LC_X12_Y12_N0 2 " "Info: 2: + IC(0.548 ns) + CELL(0.366 ns) = 0.914 ns; Loc. = LC_X12_Y12_N0; Fanout = 2; COMB Node = 'wai_t~174'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.914 ns" { ladd[1] wai_t~174 } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.246 ns) + CELL(0.319 ns) 2.479 ns wai_t\[0\] 3 REG LC_X12_Y13_N5 8 " "Info: 3: + IC(1.246 ns) + CELL(0.319 ns) = 2.479 ns; Loc. = LC_X12_Y13_N5; Fanout = 8; REG Node = 'wai_t\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.565 ns" { wai_t~174 wai_t[0] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.685 ns ( 27.63 % ) " "Info: Total cell delay = 0.685 ns ( 27.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.794 ns ( 72.37 % ) " "Info: Total interconnect delay = 1.794 ns ( 72.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "2.479 ns" { ladd[1] wai_t~174 wai_t[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.479 ns" { ladd[1] wai_t~174 wai_t[0] } { 0.000ns 0.548ns 1.246ns } { 0.000ns 0.366ns 0.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-10.107 ns - Smallest " "Info: - Smallest clock skew is -10.107 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 7.660 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 7.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clkin 1 CLK PIN_L2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { clkin } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.631 ns) + CELL(0.698 ns) 3.054 ns dir\[0\] 2 REG LC_X14_Y12_N5 22 " "Info: 2: + IC(1.631 ns) + CELL(0.698 ns) = 3.054 ns; Loc. = LC_X14_Y12_N5; Fanout = 22; REG Node = 'dir\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "2.329 ns" { clkin dir[0] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.064 ns) + CELL(0.542 ns) 7.660 ns wai_t\[0\] 3 REG LC_X12_Y13_N5 8 " "Info: 3: + IC(4.064 ns) + CELL(0.542 ns) = 7.660 ns; Loc. = LC_X12_Y13_N5; Fanout = 8; REG Node = 'wai_t\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "4.606 ns" { dir[0] wai_t[0] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.965 ns ( 25.65 % ) " "Info: Total cell delay = 1.965 ns ( 25.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.695 ns ( 74.35 % ) " "Info: Total interconnect delay = 5.695 ns ( 74.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "7.660 ns" { clkin dir[0] wai_t[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "7.660 ns" { clkin clkin~out0 dir[0] wai_t[0] } { 0.000ns 0.000ns 1.631ns 4.064ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 17.767 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 17.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clkin 1 CLK PIN_L2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 3; CLK Node = 'clkin'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { clkin } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.631 ns) + CELL(0.698 ns) 3.054 ns dir\[0\] 2 REG LC_X14_Y12_N5 22 " "Info: 2: + IC(1.631 ns) + CELL(0.698 ns) = 3.054 ns; Loc. = LC_X14_Y12_N5; Fanout = 22; REG Node = 'dir\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "2.329 ns" { clkin dir[0] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.055 ns) + CELL(0.698 ns) 7.807 ns liftor\[1\] 3 REG LC_X12_Y12_N4 16 " "Info: 3: + IC(4.055 ns) + CELL(0.698 ns) = 7.807 ns; Loc. = LC_X12_Y12_N4; Fanout = 16; REG Node = 'liftor\[1\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "4.753 ns" { dir[0] liftor[1] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.280 ns) 8.666 ns p2~2640 4 COMB LC_X13_Y12_N0 1 " "Info: 4: + IC(0.579 ns) + CELL(0.280 ns) = 8.666 ns; Loc. = LC_X13_Y12_N0; Fanout = 1; COMB Node = 'p2~2640'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.859 ns" { liftor[1] p2~2640 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.075 ns) 9.059 ns p2~2641 5 COMB LC_X13_Y12_N3 5 " "Info: 5: + IC(0.318 ns) + CELL(0.075 ns) = 9.059 ns; Loc. = LC_X13_Y12_N3; Fanout = 5; COMB Node = 'p2~2641'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.393 ns" { p2~2640 p2~2641 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.183 ns) 10.247 ns p2~2644 6 COMB LC_X13_Y13_N0 4 " "Info: 6: + IC(1.005 ns) + CELL(0.183 ns) = 10.247 ns; Loc. = LC_X13_Y13_N0; Fanout = 4; COMB Node = 'p2~2644'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.188 ns" { p2~2641 p2~2644 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.256 ns) + CELL(0.280 ns) 11.783 ns p2~2645 7 COMB LC_X13_Y15_N5 1 " "Info: 7: + IC(1.256 ns) + CELL(0.280 ns) = 11.783 ns; Loc. = LC_X13_Y15_N5; Fanout = 1; COMB Node = 'p2~2645'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.536 ns" { p2~2644 p2~2645 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.978 ns) + CELL(0.183 ns) 12.944 ns p2~2647 8 COMB LC_X14_Y14_N9 1 " "Info: 8: + IC(0.978 ns) + CELL(0.183 ns) = 12.944 ns; Loc. = LC_X14_Y14_N9; Fanout = 1; COMB Node = 'p2~2647'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.161 ns" { p2~2645 p2~2647 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.075 ns) 14.011 ns ur\[2\] 9 REG LC_X13_Y12_N4 3 " "Info: 9: + IC(0.992 ns) + CELL(0.075 ns) = 14.011 ns; Loc. = LC_X13_Y12_N4; Fanout = 3; REG Node = 'ur\[2\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.067 ns" { p2~2647 ur[2] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.280 ns) 15.275 ns rtl~118 10 COMB LC_X12_Y14_N7 2 " "Info: 10: + IC(0.984 ns) + CELL(0.280 ns) = 15.275 ns; Loc. = LC_X12_Y14_N7; Fanout = 2; COMB Node = 'rtl~118'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.264 ns" { ur[2] rtl~118 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 15.484 ns rtl~0 11 COMB LC_X12_Y14_N8 2 " "Info: 11: + IC(0.134 ns) + CELL(0.075 ns) = 15.484 ns; Loc. = LC_X12_Y14_N8; Fanout = 2; COMB Node = 'rtl~0'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.209 ns" { rtl~118 rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.949 ns) + CELL(0.280 ns) 16.713 ns p3~289 12 COMB LC_X13_Y15_N1 1 " "Info: 12: + IC(0.949 ns) + CELL(0.280 ns) = 16.713 ns; Loc. = LC_X13_Y15_N1; Fanout = 1; COMB Node = 'p3~289'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.229 ns" { rtl~0 p3~289 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.979 ns) + CELL(0.075 ns) 17.767 ns ladd\[1\] 13 REG LC_X12_Y12_N1 6 " "Info: 13: + IC(0.979 ns) + CELL(0.075 ns) = 17.767 ns; Loc. = LC_X12_Y12_N1; Fanout = 6; REG Node = 'ladd\[1\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.054 ns" { p3~289 ladd[1] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.907 ns ( 21.99 % ) " "Info: Total cell delay = 3.907 ns ( 21.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.860 ns ( 78.01 % ) " "Info: Total interconnect delay = 13.860 ns ( 78.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "17.767 ns" { clkin dir[0] liftor[1] p2~2640 p2~2641 p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~289 ladd[1] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "17.767 ns" { clkin clkin~out0 dir[0] liftor[1] p2~2640 p2~2641 p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~289 ladd[1] } { 0.000ns 0.000ns 1.631ns 4.055ns 0.579ns 0.318ns 1.005ns 1.256ns 0.978ns 0.992ns 0.984ns 0.134ns 0.949ns 0.979ns } { 0.000ns 0.725ns 0.698ns 0.698ns 0.280ns 0.075ns 0.183ns 0.280ns 0.183ns 0.075ns 0.280ns 0.075ns 0.280ns 0.075ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "7.660 ns" { clkin dir[0] wai_t[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "7.660 ns" { clkin clkin~out0 dir[0] wai_t[0] } { 0.000ns 0.000ns 1.631ns 4.064ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "17.767 ns" { clkin dir[0] liftor[1] p2~2640 p2~2641 p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~289 ladd[1] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "17.767 ns" { clkin clkin~out0 dir[0] liftor[1] p2~2640 p2~2641 p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~289 ladd[1] } { 0.000ns 0.000ns 1.631ns 4.055ns 0.579ns 0.318ns 1.005ns 1.256ns 0.978ns 0.992ns 0.984ns 0.134ns 0.949ns 0.979ns } { 0.000ns 0.725ns 0.698ns 0.698ns 0.280ns 0.075ns 0.183ns 0.280ns 0.183ns 0.075ns 0.280ns 0.075ns 0.280ns 0.075ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "2.479 ns" { ladd[1] wai_t~174 wai_t[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.479 ns" { ladd[1] wai_t~174 wai_t[0] } { 0.000ns 0.548ns 1.246ns } { 0.000ns 0.366ns 0.319ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "7.660 ns" { clkin dir[0] wai_t[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "7.660 ns" { clkin clkin~out0 dir[0] wai_t[0] } { 0.000ns 0.000ns 1.631ns 4.064ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "17.767 ns" { clkin dir[0] liftor[1] p2~2640 p2~2641 p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~289 ladd[1] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "17.767 ns" { clkin clkin~out0 dir[0] liftor[1] p2~2640 p2~2641 p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~289 ladd[1] } { 0.000ns 0.000ns 1.631ns 4.055ns 0.579ns 0.318ns 1.005ns 1.256ns 0.978ns 0.992ns 0.984ns 0.134ns 0.949ns 0.979ns } { 0.000ns 0.725ns 0.698ns 0.698ns 0.280ns 0.075ns 0.183ns 0.280ns 0.183ns 0.075ns 0.280ns 0.075ns 0.280ns 0.075ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "upin register ladd\[0\] register ladd\[0\] 114.43 MHz 8.739 ns Internal " "Info: Clock \"upin\" has Internal fmax of 114.43 MHz between source register \"ladd\[0\]\" and destination register \"ladd\[0\]\" (period= 8.739 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.733 ns + Longest register register " "Info: + Longest register to register delay is 4.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ladd\[0\] 1 REG LC_X12_Y12_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y12_N5; Fanout = 4; REG Node = 'ladd\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { ladd[0] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.368 ns) + CELL(0.075 ns) 2.443 ns Mux~727 2 COMB LC_X13_Y14_N1 1 " "Info: 2: + IC(2.368 ns) + CELL(0.075 ns) = 2.443 ns; Loc. = LC_X13_Y14_N1; Fanout = 1; COMB Node = 'Mux~727'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "2.443 ns" { ladd[0] Mux~727 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.183 ns) 2.966 ns Mux~729 3 COMB LC_X13_Y14_N2 1 " "Info: 3: + IC(0.340 ns) + CELL(0.183 ns) = 2.966 ns; Loc. = LC_X13_Y14_N2; Fanout = 1; COMB Node = 'Mux~729'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.523 ns" { Mux~727 Mux~729 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.977 ns) + CELL(0.075 ns) 4.018 ns Mux~731 4 COMB LC_X12_Y12_N2 1 " "Info: 4: + IC(0.977 ns) + CELL(0.075 ns) = 4.018 ns; Loc. = LC_X12_Y12_N2; Fanout = 1; COMB Node = 'Mux~731'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.052 ns" { Mux~729 Mux~731 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.366 ns) 4.733 ns ladd\[0\] 5 REG LC_X12_Y12_N5 4 " "Info: 5: + IC(0.349 ns) + CELL(0.366 ns) = 4.733 ns; Loc. = LC_X12_Y12_N5; Fanout = 4; REG Node = 'ladd\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.715 ns" { Mux~731 ladd[0] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.699 ns ( 14.77 % ) " "Info: Total cell delay = 0.699 ns ( 14.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.034 ns ( 85.23 % ) " "Info: Total interconnect delay = 4.034 ns ( 85.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "4.733 ns" { ladd[0] Mux~727 Mux~729 Mux~731 ladd[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.733 ns" { ladd[0] Mux~727 Mux~729 Mux~731 ladd[0] } { 0.000ns 2.368ns 0.340ns 0.977ns 0.349ns } { 0.000ns 0.075ns 0.183ns 0.075ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.417 ns - Smallest " "Info: - Smallest clock skew is -3.417 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "upin destination 6.955 ns + Shortest register " "Info: + Shortest clock path from clock \"upin\" to destination register is 6.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns upin 1 CLK PIN_M22 5 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M22; Fanout = 5; CLK Node = 'upin'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { upin } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.466 ns) + CELL(0.366 ns) 2.557 ns p2~2657 2 COMB LC_X13_Y13_N2 3 " "Info: 2: + IC(1.466 ns) + CELL(0.366 ns) = 2.557 ns; Loc. = LC_X13_Y13_N2; Fanout = 3; COMB Node = 'p2~2657'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.832 ns" { upin p2~2657 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.312 ns) + CELL(0.075 ns) 2.944 ns p2~2664 3 COMB LC_X13_Y13_N8 1 " "Info: 3: + IC(0.312 ns) + CELL(0.075 ns) = 2.944 ns; Loc. = LC_X13_Y13_N8; Fanout = 1; COMB Node = 'p2~2664'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.387 ns" { p2~2657 p2~2664 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 3.153 ns ur\[6\] 4 REG LC_X13_Y13_N9 4 " "Info: 4: + IC(0.134 ns) + CELL(0.075 ns) = 3.153 ns; Loc. = LC_X13_Y13_N9; Fanout = 4; REG Node = 'ur\[6\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.209 ns" { p2~2664 ur[6] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.945 ns) + CELL(0.280 ns) 4.378 ns rtl~0 5 COMB LC_X12_Y14_N8 2 " "Info: 5: + IC(0.945 ns) + CELL(0.280 ns) = 4.378 ns; Loc. = LC_X12_Y14_N8; Fanout = 2; COMB Node = 'rtl~0'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.225 ns" { ur[6] rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 4.587 ns p3~287 6 COMB LC_X12_Y14_N9 2 " "Info: 6: + IC(0.134 ns) + CELL(0.075 ns) = 4.587 ns; Loc. = LC_X12_Y14_N9; Fanout = 2; COMB Node = 'p3~287'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.209 ns" { rtl~0 p3~287 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.967 ns) + CELL(0.366 ns) 5.920 ns p3~290 7 COMB LC_X12_Y13_N2 1 " "Info: 7: + IC(0.967 ns) + CELL(0.366 ns) = 5.920 ns; Loc. = LC_X12_Y13_N2; Fanout = 1; COMB Node = 'p3~290'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.333 ns" { p3~287 p3~290 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.960 ns) + CELL(0.075 ns) 6.955 ns ladd\[0\] 8 REG LC_X12_Y12_N5 4 " "Info: 8: + IC(0.960 ns) + CELL(0.075 ns) = 6.955 ns; Loc. = LC_X12_Y12_N5; Fanout = 4; REG Node = 'ladd\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.035 ns" { p3~290 ladd[0] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.037 ns ( 29.29 % ) " "Info: Total cell delay = 2.037 ns ( 29.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.918 ns ( 70.71 % ) " "Info: Total interconnect delay = 4.918 ns ( 70.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "6.955 ns" { upin p2~2657 p2~2664 ur[6] rtl~0 p3~287 p3~290 ladd[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "6.955 ns" { upin upin~out0 p2~2657 p2~2664 ur[6] rtl~0 p3~287 p3~290 ladd[0] } { 0.000ns 0.000ns 1.466ns 0.312ns 0.134ns 0.945ns 0.134ns 0.967ns 0.960ns } { 0.000ns 0.725ns 0.366ns 0.075ns 0.075ns 0.280ns 0.075ns 0.366ns 0.075ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "upin source 10.372 ns - Longest register " "Info: - Longest clock path from clock \"upin\" to source register is 10.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns upin 1 CLK PIN_M22 5 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M22; Fanout = 5; CLK Node = 'upin'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { upin } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.467 ns) + CELL(0.366 ns) 2.558 ns p2~2644 2 COMB LC_X13_Y13_N0 4 " "Info: 2: + IC(1.467 ns) + CELL(0.366 ns) = 2.558 ns; Loc. = LC_X13_Y13_N0; Fanout = 4; COMB Node = 'p2~2644'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.833 ns" { upin p2~2644 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.256 ns) + CELL(0.280 ns) 4.094 ns p2~2645 3 COMB LC_X13_Y15_N5 1 " "Info: 3: + IC(1.256 ns) + CELL(0.280 ns) = 4.094 ns; Loc. = LC_X13_Y15_N5; Fanout = 1; COMB Node = 'p2~2645'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.536 ns" { p2~2644 p2~2645 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.978 ns) + CELL(0.183 ns) 5.255 ns p2~2647 4 COMB LC_X14_Y14_N9 1 " "Info: 4: + IC(0.978 ns) + CELL(0.183 ns) = 5.255 ns; Loc. = LC_X14_Y14_N9; Fanout = 1; COMB Node = 'p2~2647'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.161 ns" { p2~2645 p2~2647 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.075 ns) 6.322 ns ur\[2\] 5 REG LC_X13_Y12_N4 3 " "Info: 5: + IC(0.992 ns) + CELL(0.075 ns) = 6.322 ns; Loc. = LC_X13_Y12_N4; Fanout = 3; REG Node = 'ur\[2\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.067 ns" { p2~2647 ur[2] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.280 ns) 7.586 ns rtl~118 6 COMB LC_X12_Y14_N7 2 " "Info: 6: + IC(0.984 ns) + CELL(0.280 ns) = 7.586 ns; Loc. = LC_X12_Y14_N7; Fanout = 2; COMB Node = 'rtl~118'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.264 ns" { ur[2] rtl~118 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 7.795 ns rtl~0 7 COMB LC_X12_Y14_N8 2 " "Info: 7: + IC(0.134 ns) + CELL(0.075 ns) = 7.795 ns; Loc. = LC_X12_Y14_N8; Fanout = 2; COMB Node = 'rtl~0'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.209 ns" { rtl~118 rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 8.004 ns p3~287 8 COMB LC_X12_Y14_N9 2 " "Info: 8: + IC(0.134 ns) + CELL(0.075 ns) = 8.004 ns; Loc. = LC_X12_Y14_N9; Fanout = 2; COMB Node = 'p3~287'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "0.209 ns" { rtl~0 p3~287 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.967 ns) + CELL(0.366 ns) 9.337 ns p3~290 9 COMB LC_X12_Y13_N2 1 " "Info: 9: + IC(0.967 ns) + CELL(0.366 ns) = 9.337 ns; Loc. = LC_X12_Y13_N2; Fanout = 1; COMB Node = 'p3~290'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.333 ns" { p3~287 p3~290 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.960 ns) + CELL(0.075 ns) 10.372 ns ladd\[0\] 10 REG LC_X12_Y12_N5 4 " "Info: 10: + IC(0.960 ns) + CELL(0.075 ns) = 10.372 ns; Loc. = LC_X12_Y12_N5; Fanout = 4; REG Node = 'ladd\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "1.035 ns" { p3~290 ladd[0] } "NODE_NAME" } "" } } { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 24.10 % ) " "Info: Total cell delay = 2.500 ns ( 24.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.872 ns ( 75.90 % ) " "Info: Total interconnect delay = 7.872 ns ( 75.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "10.372 ns" { upin p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~287 p3~290 ladd[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "10.372 ns" { upin upin~out0 p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~287 p3~290 ladd[0] } { 0.000ns 0.000ns 1.467ns 1.256ns 0.978ns 0.992ns 0.984ns 0.134ns 0.134ns 0.967ns 0.960ns } { 0.000ns 0.725ns 0.366ns 0.280ns 0.183ns 0.075ns 0.280ns 0.075ns 0.075ns 0.366ns 0.075ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "6.955 ns" { upin p2~2657 p2~2664 ur[6] rtl~0 p3~287 p3~290 ladd[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "6.955 ns" { upin upin~out0 p2~2657 p2~2664 ur[6] rtl~0 p3~287 p3~290 ladd[0] } { 0.000ns 0.000ns 1.466ns 0.312ns 0.134ns 0.945ns 0.134ns 0.967ns 0.960ns } { 0.000ns 0.725ns 0.366ns 0.075ns 0.075ns 0.280ns 0.075ns 0.366ns 0.075ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "10.372 ns" { upin p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~287 p3~290 ladd[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "10.372 ns" { upin upin~out0 p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~287 p3~290 ladd[0] } { 0.000ns 0.000ns 1.467ns 1.256ns 0.978ns 0.992ns 0.984ns 0.134ns 0.134ns 0.967ns 0.960ns } { 0.000ns 0.725ns 0.366ns 0.280ns 0.183ns 0.075ns 0.280ns 0.075ns 0.075ns 0.366ns 0.075ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.589 ns + " "Info: + Micro setup delay of destination is 0.589 ns" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "4.733 ns" { ladd[0] Mux~727 Mux~729 Mux~731 ladd[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.733 ns" { ladd[0] Mux~727 Mux~729 Mux~731 ladd[0] } { 0.000ns 2.368ns 0.340ns 0.977ns 0.349ns } { 0.000ns 0.075ns 0.183ns 0.075ns 0.366ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "6.955 ns" { upin p2~2657 p2~2664 ur[6] rtl~0 p3~287 p3~290 ladd[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "6.955 ns" { upin upin~out0 p2~2657 p2~2664 ur[6] rtl~0 p3~287 p3~290 ladd[0] } { 0.000ns 0.000ns 1.466ns 0.312ns 0.134ns 0.945ns 0.134ns 0.967ns 0.960ns } { 0.000ns 0.725ns 0.366ns 0.075ns 0.075ns 0.280ns 0.075ns 0.366ns 0.075ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "10.372 ns" { upin p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~287 p3~290 ladd[0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "10.372 ns" { upin upin~out0 p2~2644 p2~2645 p2~2647 ur[2] rtl~118 rtl~0 p3~287 p3~290 ladd[0] } { 0.000ns 0.000ns 1.467ns 1.256ns 0.978ns 0.992ns 0.984ns 0.134ns 0.134ns 0.967ns 0.960ns } { 0.000ns 0.725ns 0.366ns 0.280ns 0.183ns 0.075ns 0.280ns 0.075ns 0.075ns 0.366ns 0.075ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}