lift.tan.qmsg

用fpga控制电梯,实现五层电梯的升降控制,运用vhdl编辑程序.

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 7 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "upin " "Info: Assuming node \"upin\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "st_ch " "Info: Assuming node \"st_ch\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 10 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "downin " "Info: Assuming node \"downin\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 9 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "51 " "Warning: Found 51 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ur\[5\] " "Info: Detected ripple clock \"ur\[5\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "ur\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ur\[6\] " "Info: Detected ripple clock \"ur\[6\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "ur\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ur\[1\] " "Info: Detected ripple clock \"ur\[1\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "ur\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ur\[3\] " "Info: Detected ripple clock \"ur\[3\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "ur\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ur\[2\] " "Info: Detected ripple clock \"ur\[2\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "ur\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ur\[4\] " "Info: Detected ripple clock \"ur\[4\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "ur\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2663 " "Info: Detected gated clock \"p2~2663\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2663" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2661 " "Info: Detected gated clock \"p2~2661\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2661" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2658 " "Info: Detected gated clock \"p2~2658\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2658" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2657 " "Info: Detected gated clock \"p2~2657\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2657" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2656 " "Info: Detected gated clock \"p2~2656\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2656" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2653 " "Info: Detected gated clock \"p2~2653\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2653" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2651 " "Info: Detected gated clock \"p2~2651\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2651" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2649 " "Info: Detected gated clock \"p2~2649\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2649" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2646 " "Info: Detected gated clock \"p2~2646\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2646" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2645 " "Info: Detected gated clock \"p2~2645\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2645" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2644 " "Info: Detected gated clock \"p2~2644\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2644" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "liftor\[1\]~614 " "Info: Detected gated clock \"liftor\[1\]~614\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "liftor\[1\]~614" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2642 " "Info: Detected gated clock \"p2~2642\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2642" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2641 " "Info: Detected gated clock \"p2~2641\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2641" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2640 " "Info: Detected gated clock \"p2~2640\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2640" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2638 " "Info: Detected gated clock \"p2~2638\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2638" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2637 " "Info: Detected gated clock \"p2~2637\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2637" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2636 " "Info: Detected gated clock \"p2~2636\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2636" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2635 " "Info: Detected gated clock \"p2~2635\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2635" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2634 " "Info: Detected gated clock \"p2~2634\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2634" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p3~290 " "Info: Detected gated clock \"p3~290\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p3~290" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p3~288 " "Info: Detected gated clock \"p3~288\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p3~288" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2647 " "Info: Detected gated clock \"p2~2647\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2647" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2652 " "Info: Detected gated clock \"p2~2652\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2652" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p3~286 " "Info: Detected gated clock \"p3~286\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p3~286" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2662 " "Info: Detected gated clock \"p2~2662\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2662" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2664 " "Info: Detected gated clock \"p2~2664\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2664" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p3~285 " "Info: Detected gated clock \"p3~285\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p3~285" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p2~2655 " "Info: Detected gated clock \"p2~2655\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p2~2655" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p3~284 " "Info: Detected gated clock \"p3~284\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p3~284" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~0 " "Info: Detected gated clock \"rtl~0\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "rtl~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~118 " "Info: Detected gated clock \"rtl~118\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "rtl~118" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "add~264 " "Info: Detected gated clock \"add~264\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "add~264" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "dir\[2\] " "Info: Detected ripple clock \"dir\[2\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 40 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "dir\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "dir\[1\] " "Info: Detected ripple clock \"dir\[1\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 40 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "dir\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "liftor\[2\] " "Info: Detected ripple clock \"liftor\[2\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "liftor\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "add~260 " "Info: Detected gated clock \"add~260\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "add~260" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "liftor\[1\] " "Info: Detected ripple clock \"liftor\[1\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "liftor\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "liftor\[0\] " "Info: Detected ripple clock \"liftor\[0\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "liftor\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p3~289 " "Info: Detected gated clock \"p3~289\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p3~289" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "p3~287 " "Info: Detected gated clock \"p3~287\" as buffer" {  } { { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "p3~287" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "dir\[0\] " "Info: Detected ripple clock \"dir\[0\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 40 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "dir\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "wai_t\[2\] " "Info: Detected ripple clock \"wai_t\[2\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "wai_t\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "wai_t\[1\] " "Info: Detected ripple clock \"wai_t\[1\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "wai_t\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "wai_t\[0\] " "Info: Detected ripple clock \"wai_t\[0\]\" as buffer" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "wai_t\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}