ushow_top.v

来自「vga的fpga实现」· Verilog 代码 · 共 19 行

`timescale 1ns/1ns
module vga_control_top;
wire vs,hs,blank,r,g,b;
reg clk,reset,mode;
always
begin
    #(10)clk<=~clk;
end
vga_control vc(reset,clk,mode,vs,hs,blank,r,g,b);
initial
begin
    clk<=1;
    reset<=0;
    mode<=1;
    #(10)reset=1;
    //vs=1;
    //hs=1;
end
endmodule