_primary.vhd

来自「vga的fpga实现」· VHDL 代码 · 共 26 行

library verilog;
use verilog.vl_types.all;
entity vga_control is
    generic(
        h_vidio         : integer := 0;
        h_front         : integer := 1;
        h_sync          : integer := 2;
        h_back          : integer := 3;
        v_vidio         : integer := 0;
        v_front         : integer := 1;
        v_sync          : integer := 2;
        v_back          : integer := 3
    );
    port(
        reset           : in     vl_logic;
        clk             : in     vl_logic;
        mode            : in     vl_logic;
        vs              : out    vl_logic;
        hs              : out    vl_logic;
        blank           : out    vl_logic;
        r               : out    vl_logic;
        g               : out    vl_logic;
        b               : out    vl_logic
    );
end vga_control;