vga_driver.v

vga的fpga实现

module vga_dirver(reset,clk,mode,vs,hs,blank,r,g,b);
input clk,reset,mode;
output vs,hs,blank,r,g,b;
reg[10:1] h_cnt,v_cnt;
reg[3:1] color;
reg vs,hs;
parameter 
  h_vidio =2'b00,
  h_front =2'b01,
  h_sync  =2'b10,
  h_back  =2'b11;
parameter 
  v_vidio =2'b00,
  v_front =2'b01,
  v_sync  =2'b10,
  v_back  =2'b11;
reg [2:1] h_state,v_state;

assign blank=hs&vs;  //复合消隐信号
assign {r,g,b}=color;

always @(posedge clk)
begin
  if(reset==0)
  begin
    //vs=1;
    //hs=1;
    h_cnt=0;
    v_cnt=0;
  end
  h_cnt=h_cnt+1'b1;
  if(h_cnt==800)    //800个象素，640个有效
    h_cnt=0;
  if (h_cnt==0)       h_state=h_vidio;
  else if(h_cnt==640) h_state=h_front;
  else if(h_cnt==664)  //开始行同步 
  begin 
    h_state=h_sync;
    v_cnt=v_cnt+1'b1;   //行同步来时，场计数器加一
    if(v_cnt==525) v_cnt=0;
  end
  else if(h_cnt==760) h_state=h_back;
  
  if(v_cnt==0) v_state=v_vidio;
  else if(v_cnt==480) v_state=v_front;
  else if(v_cnt==498) v_state=v_sync;
  else if(v_cnt==500) v_state=v_back;

  if(mode==0)  //横彩条
  begin
    if(v_cnt[5:1]<3) color ='b111;
	else if(v_cnt[5:1]<7)color ='b110;
	else if(v_cnt[5:1]<11)color ='b101;
	else if(v_cnt[5:1]<15)color ='b100;
	else if(v_cnt[5:1]<19)color ='b011;
	else if(v_cnt[5:1]<23)color ='b010;
	else if(v_cnt[5:1]<27)color ='b001;
	else color='b000;
  end

  if(mode==1)  //竖彩条
  begin
    if(h_cnt[5:1]<3) color ='b111;
    else if(h_cnt[5:1]<7)color ='b110;
    else if(h_cnt[5:1]<11)color ='b101;
    else if(h_cnt[5:1]<15)color ='b100;
    else if(h_cnt[5:1]<19)color ='b011;
    else if(h_cnt[5:1]<23)color ='b010;
    else if(h_cnt[5:1]<27)color ='b001;
    else color ='b000;
  end
end

always @(h_state or v_state)
begin
  case (h_state)
    h_vidio: hs=0;
    h_front: hs=0;
    h_sync:  hs=1;
    h_back:  hs=0;
  endcase
  case (v_state)
    v_vidio: vs=0;
    v_front: vs=0;
	v_sync:  vs=1;
	v_back:  vs=0;
  endcase
end
endmodule