ym4_1.map.rpt

7段数码是纯组合电路

+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Total logic elements                        ; 15       ;
;     -- Combinational with no register       ; 15       ;
;     -- Register only                        ; 0        ;
;     -- Combinational with a register        ; 0        ;
;                                             ;          ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 5        ;
;     -- 3 input functions                    ; 10       ;
;     -- 2 input functions                    ; 0        ;
;     -- 1 input functions                    ; 0        ;
;     -- 0 input functions                    ; 0        ;
;                                             ;          ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 15       ;
;     -- arithmetic mode                      ; 0        ;
;     -- qfbk mode                            ; 0        ;
;     -- register cascade mode                ; 0        ;
;     -- synchronous clear/load mode          ; 0        ;
;     -- asynchronous clear/load mode         ; 0        ;
;                                             ;          ;
; Total registers                             ; 0        ;
; I/O pins                                    ; 12       ;
; Maximum fan-out node                        ; ledin[1] ;
; Maximum fan-out                             ; 8        ;
; Total fan-out                               ; 57       ;
; Average fan-out                             ; 2.11     ;
+---------------------------------------------+----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |ym4_1                     ; 15 (15)     ; 0            ; 0           ; 12   ; 0            ; 15 (15)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ym4_1              ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; ledout[0]$latch                                    ; Mux7                ; yes                    ;
; ledout[1]$latch                                    ; Mux7                ; yes                    ;
; ledout[2]$latch                                    ; Mux7                ; yes                    ;
; ledout[3]$latch                                    ; Mux7                ; yes                    ;
; ledout[4]$latch                                    ; Mux7                ; yes                    ;
; ledout[5]$latch                                    ; Mux7                ; yes                    ;
; ledout[6]$latch                                    ; Mux7                ; yes                    ;
; Number of user-specified and inferred latches = 7  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Mon Dec 03 16:30:10 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ym4_1 -c ym4_1
Info: Found 2 design units, including 1 entities, in source file ym4_1.vhd
    Info: Found design unit 1: ym4_1-leds
    Info: Found entity 1: ym4_1
Info: Elaborating entity "ym4_1" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at ym4_1.vhd(8): inferring latch(es) for signal or variable "ledout", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "ledout[0]" at ym4_1.vhd(8)
Info (10041): Inferred latch for "ledout[1]" at ym4_1.vhd(8)
Info (10041): Inferred latch for "ledout[2]" at ym4_1.vhd(8)
Info (10041): Inferred latch for "ledout[3]" at ym4_1.vhd(8)
Info (10041): Inferred latch for "ledout[4]" at ym4_1.vhd(8)
Info (10041): Inferred latch for "ledout[5]" at ym4_1.vhd(8)
Info (10041): Inferred latch for "ledout[6]" at ym4_1.vhd(8)
Info (10041): Inferred latch for "ledout[7]" at ym4_1.vhd(8)
Warning: Latch ledout[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ledin[1]
Warning: Latch ledout[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ledin[2]
Warning: Latch ledout[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ledin[1]
Warning: Latch ledout[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ledin[1]
Warning: Latch ledout[4]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ledin[1]
Warning: Latch ledout[5]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ledin[1]
Warning: Latch ledout[6]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ledin[1]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "ledout[7]" stuck at GND
Info: Implemented 27 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 8 output pins
    Info: Implemented 15 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings
    Info: Allocated 146 megabytes of memory during processing
    Info: Processing ended: Mon Dec 03 16:30:13 2007
    Info: Elapsed time: 00:00:03