prev_cmp_ym4_1.tan.qmsg

7段数码是纯组合电路

{ "Info" "ITDB_TSU_RESULT" "ledout\[0\]\$latch ledin\[0\] ledin\[0\] 4.429 ns register " "Info: tsu for register \"ledout\[0\]\$latch\" (data pin = \"ledin\[0\]\", clock pin = \"ledin\[0\]\") is 4.429 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.443 ns + Longest pin register " "Info: + Longest pin to register delay is 6.443 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ledin\[0\] 1 CLK PIN_11 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'ledin\[0\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[0] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.532 ns) + CELL(0.442 ns) 6.443 ns ledout\[0\]\$latch 2 REG LC_X1_Y9_N2 6 " "Info: 2: + IC(4.532 ns) + CELL(0.442 ns) = 6.443 ns; Loc. = LC_X1_Y9_N2; Fanout = 6; REG Node = 'ledout\[0\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.974 ns" { ledin[0] ledout[0]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 29.66 % ) " "Info: Total cell delay = 1.911 ns ( 29.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.532 ns ( 70.34 % ) " "Info: Total interconnect delay = 4.532 ns ( 70.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.443 ns" { ledin[0] ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "6.443 ns" { ledin[0] ledin[0]~out0 ledout[0]$latch } { 0.000ns 0.000ns 4.532ns } { 0.000ns 1.469ns 0.442ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.842 ns + " "Info: + Micro setup delay of destination is 0.842 ns" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ledin\[0\] destination 2.856 ns - Shortest register " "Info: - Shortest clock path from clock \"ledin\[0\]\" to destination register is 2.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ledin\[0\] 1 CLK PIN_11 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'ledin\[0\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[0] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.799 ns) + CELL(0.292 ns) 2.560 ns Mux1~26 2 COMB LC_X1_Y9_N1 1 " "Info: 2: + IC(0.799 ns) + CELL(0.292 ns) = 2.560 ns; Loc. = LC_X1_Y9_N1; Fanout = 1; COMB Node = 'Mux1~26'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { ledin[0] Mux1~26 } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.856 ns ledout\[0\]\$latch 3 REG LC_X1_Y9_N2 6 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 2.856 ns; Loc. = LC_X1_Y9_N2; Fanout = 6; REG Node = 'ledout\[0\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Mux1~26 ledout[0]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.875 ns ( 65.65 % ) " "Info: Total cell delay = 1.875 ns ( 65.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns ( 34.35 % ) " "Info: Total interconnect delay = 0.981 ns ( 34.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { ledin[0] Mux1~26 ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { ledin[0] ledin[0]~out0 Mux1~26 ledout[0]$latch } { 0.000ns 0.000ns 0.799ns 0.182ns } { 0.000ns 1.469ns 0.292ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.443 ns" { ledin[0] ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "6.443 ns" { ledin[0] ledin[0]~out0 ledout[0]$latch } { 0.000ns 0.000ns 4.532ns } { 0.000ns 1.469ns 0.442ns } "" } } { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { ledin[0] Mux1~26 ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { ledin[0] ledin[0]~out0 Mux1~26 ledout[0]$latch } { 0.000ns 0.000ns 0.799ns 0.182ns } { 0.000ns 1.469ns 0.292ns 0.114ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "ledin\[2\] ledout\[3\] ledout\[0\]\$latch 8.411 ns register " "Info: tco from clock \"ledin\[2\]\" to destination pin \"ledout\[3\]\" through register \"ledout\[0\]\$latch\" is 8.411 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ledin\[2\] source 3.954 ns + Longest register " "Info: + Longest clock path from clock \"ledin\[2\]\" to source register is 3.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ledin\[2\] 1 CLK PIN_16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 1; CLK Node = 'ledin\[2\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[2] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.599 ns) + CELL(0.590 ns) 3.658 ns Mux1~26 2 COMB LC_X1_Y9_N1 1 " "Info: 2: + IC(1.599 ns) + CELL(0.590 ns) = 3.658 ns; Loc. = LC_X1_Y9_N1; Fanout = 1; COMB Node = 'Mux1~26'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.189 ns" { ledin[2] Mux1~26 } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.954 ns ledout\[0\]\$latch 3 REG LC_X1_Y9_N2 6 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 3.954 ns; Loc. = LC_X1_Y9_N2; Fanout = 6; REG Node = 'ledout\[0\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Mux1~26 ledout[0]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.173 ns ( 54.96 % ) " "Info: Total cell delay = 2.173 ns ( 54.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.781 ns ( 45.04 % ) " "Info: Total interconnect delay = 1.781 ns ( 45.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.954 ns" { ledin[2] Mux1~26 ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "3.954 ns" { ledin[2] ledin[2]~out0 Mux1~26 ledout[0]$latch } { 0.000ns 0.000ns 1.599ns 0.182ns } { 0.000ns 1.469ns 0.590ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.457 ns + Longest register pin " "Info: + Longest register to pin delay is 4.457 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ledout\[0\]\$latch 1 REG LC_X1_Y9_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y9_N2; Fanout = 6; REG Node = 'ledout\[0\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledout[0]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.349 ns) + CELL(2.108 ns) 4.457 ns ledout\[3\] 2 PIN PIN_134 0 " "Info: 2: + IC(2.349 ns) + CELL(2.108 ns) = 4.457 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'ledout\[3\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.457 ns" { ledout[0]$latch ledout[3] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 47.30 % ) " "Info: Total cell delay = 2.108 ns ( 47.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.349 ns ( 52.70 % ) " "Info: Total interconnect delay = 2.349 ns ( 52.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.457 ns" { ledout[0]$latch ledout[3] } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "4.457 ns" { ledout[0]$latch ledout[3] } { 0.000ns 2.349ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.954 ns" { ledin[2] Mux1~26 ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "3.954 ns" { ledin[2] ledin[2]~out0 Mux1~26 ledout[0]$latch } { 0.000ns 0.000ns 1.599ns 0.182ns } { 0.000ns 1.469ns 0.590ns 0.114ns } "" } } { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.457 ns" { ledout[0]$latch ledout[3] } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "4.457 ns" { ledout[0]$latch ledout[3] } { 0.000ns 2.349ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "ledout\[0\]\$latch ledin\[0\] ledin\[2\] -2.489 ns register " "Info: th for register \"ledout\[0\]\$latch\" (data pin = \"ledin\[0\]\", clock pin = \"ledin\[2\]\") is -2.489 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ledin\[2\] destination 3.954 ns + Longest register " "Info: + Longest clock path from clock \"ledin\[2\]\" to destination register is 3.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ledin\[2\] 1 CLK PIN_16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 1; CLK Node = 'ledin\[2\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[2] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.599 ns) + CELL(0.590 ns) 3.658 ns Mux1~26 2 COMB LC_X1_Y9_N1 1 " "Info: 2: + IC(1.599 ns) + CELL(0.590 ns) = 3.658 ns; Loc. = LC_X1_Y9_N1; Fanout = 1; COMB Node = 'Mux1~26'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.189 ns" { ledin[2] Mux1~26 } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.954 ns ledout\[0\]\$latch 3 REG LC_X1_Y9_N2 6 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 3.954 ns; Loc. = LC_X1_Y9_N2; Fanout = 6; REG Node = 'ledout\[0\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Mux1~26 ledout[0]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.173 ns ( 54.96 % ) " "Info: Total cell delay = 2.173 ns ( 54.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.781 ns ( 45.04 % ) " "Info: Total interconnect delay = 1.781 ns ( 45.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.954 ns" { ledin[2] Mux1~26 ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "3.954 ns" { ledin[2] ledin[2]~out0 Mux1~26 ledout[0]$latch } { 0.000ns 0.000ns 1.599ns 0.182ns } { 0.000ns 1.469ns 0.590ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.443 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.443 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ledin\[0\] 1 CLK PIN_11 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 2; CLK Node = 'ledin\[0\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[0] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.532 ns) + CELL(0.442 ns) 6.443 ns ledout\[0\]\$latch 2 REG LC_X1_Y9_N2 6 " "Info: 2: + IC(4.532 ns) + CELL(0.442 ns) = 6.443 ns; Loc. = LC_X1_Y9_N2; Fanout = 6; REG Node = 'ledout\[0\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.974 ns" { ledin[0] ledout[0]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 29.66 % ) " "Info: Total cell delay = 1.911 ns ( 29.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.532 ns ( 70.34 % ) " "Info: Total interconnect delay = 4.532 ns ( 70.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.443 ns" { ledin[0] ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "6.443 ns" { ledin[0] ledin[0]~out0 ledout[0]$latch } { 0.000ns 0.000ns 4.532ns } { 0.000ns 1.469ns 0.442ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.954 ns" { ledin[2] Mux1~26 ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "3.954 ns" { ledin[2] ledin[2]~out0 Mux1~26 ledout[0]$latch } { 0.000ns 0.000ns 1.599ns 0.182ns } { 0.000ns 1.469ns 0.590ns 0.114ns } "" } } { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.443 ns" { ledin[0] ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "6.443 ns" { ledin[0] ledin[0]~out0 ledout[0]$latch } { 0.000ns 0.000ns 4.532ns } { 0.000ns 1.469ns 0.442ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 03 16:21:43 2007 " "Info: Processing ended: Mon Dec 03 16:21:43 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}