prev_cmp_ym4_1.qmsg

7段数码是纯组合电路

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 03 16:37:05 2007 " "Info: Processing started: Mon Dec 03 16:37:05 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ym4_1 -c ym4_1 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ym4_1 -c ym4_1 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ym4_1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ym4_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ym4_1-leds " "Info: Found design unit 1: ym4_1-leds" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 6 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ym4_1 " "Info: Found entity 1: ym4_1" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "E:/20044693/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ym4_1 " "Info: Elaborating entity \"ym4_1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ledout ym4_1.vhd(8) " "Warning (10631): VHDL Process Statement warning at ym4_1.vhd(8): inferring latch(es) for signal or variable \"ledout\", which holds its previous value in one or more paths through the process" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ledout\[0\] ym4_1.vhd(8) " "Info (10041): Inferred latch for \"ledout\[0\]\" at ym4_1.vhd(8)" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ledout\[1\] ym4_1.vhd(8) " "Info (10041): Inferred latch for \"ledout\[1\]\" at ym4_1.vhd(8)" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ledout\[2\] ym4_1.vhd(8) " "Info (10041): Inferred latch for \"ledout\[2\]\" at ym4_1.vhd(8)" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ledout\[3\] ym4_1.vhd(8) " "Info (10041): Inferred latch for \"ledout\[3\]\" at ym4_1.vhd(8)" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ledout\[4\] ym4_1.vhd(8) " "Info (10041): Inferred latch for \"ledout\[4\]\" at ym4_1.vhd(8)" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ledout\[5\] ym4_1.vhd(8) " "Info (10041): Inferred latch for \"ledout\[5\]\" at ym4_1.vhd(8)" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ledout\[6\] ym4_1.vhd(8) " "Info (10041): Inferred latch for \"ledout\[6\]\" at ym4_1.vhd(8)" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ledout\[7\] ym4_1.vhd(8) " "Info (10041): Inferred latch for \"ledout\[7\]\" at ym4_1.vhd(8)" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/eda_tool/altera7.1/quartus/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/eda_tool/altera7.1/quartus/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "d:/eda_tool/altera7.1/quartus/libraries/megafunctions/lpm_mux.tdf" 74 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux0 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux0\"" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_1hc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_1hc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_1hc " "Info: Found entity 1: mux_1hc" {  } { { "db/mux_1hc.tdf" "" { Text "E:/20044693/db/mux_1hc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux1 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux1\"" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux2 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux2\"" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux3 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux3\"" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux4 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux4\"" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux5 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux5\"" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux6 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux6\"" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux7 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux7\"" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux8 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux8\"" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_hfc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_hfc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_hfc " "Info: Found entity 1: mux_hfc" {  } { { "db/mux_hfc.tdf" "" { Text "E:/20044693/db/mux_hfc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux9 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux9\"" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 1  Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "151 " "Info: Allocated 151 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 03 16:37:07 2007 " "Info: Processing ended: Mon Dec 03 16:37:07 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}