ym4_1.sim.rpt

7段数码是纯组合电路

The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------+
; Complete 1/0-Value Coverage                     ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                     ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+
; Node Name                                                   ; Output Port Name                                            ; Output Port Type ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+
; |ym4_1|ledout[0]$latch                                      ; |ym4_1|ledout[0]$latch                                      ; out              ;
; |ym4_1|ledout[1]$latch                                      ; |ym4_1|ledout[1]$latch                                      ; out              ;
; |ym4_1|ledout[2]$latch                                      ; |ym4_1|ledout[2]$latch                                      ; out              ;
; |ym4_1|ledout[3]$latch                                      ; |ym4_1|ledout[3]$latch                                      ; out              ;
; |ym4_1|ledout[4]$latch                                      ; |ym4_1|ledout[4]$latch                                      ; out              ;
; |ym4_1|ledout[5]$latch                                      ; |ym4_1|ledout[5]$latch                                      ; out              ;
; |ym4_1|ledout[6]$latch                                      ; |ym4_1|ledout[6]$latch                                      ; out              ;
; |ym4_1|ledout[7]$latch                                      ; |ym4_1|ledout[7]$latch                                      ; out              ;
; |ym4_1|ledin[0]                                             ; |ym4_1|ledin[0]                                             ; out              ;
; |ym4_1|ledin[1]                                             ; |ym4_1|ledin[1]                                             ; out              ;
; |ym4_1|ledin[2]                                             ; |ym4_1|ledin[2]                                             ; out              ;
; |ym4_1|ledin[3]                                             ; |ym4_1|ledin[3]                                             ; out              ;
; |ym4_1|ledout[0]                                            ; |ym4_1|ledout[0]                                            ; pin_out          ;
; |ym4_1|ledout[1]                                            ; |ym4_1|ledout[1]                                            ; pin_out          ;
; |ym4_1|ledout[2]                                            ; |ym4_1|ledout[2]                                            ; pin_out          ;
; |ym4_1|ledout[3]                                            ; |ym4_1|ledout[3]                                            ; pin_out          ;
; |ym4_1|ledout[4]                                            ; |ym4_1|ledout[4]                                            ; pin_out          ;
; |ym4_1|ledout[5]                                            ; |ym4_1|ledout[5]                                            ; pin_out          ;
; |ym4_1|ledout[6]                                            ; |ym4_1|ledout[6]                                            ; pin_out          ;
; |ym4_1|ledout[7]                                            ; |ym4_1|ledout[7]                                            ; pin_out          ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|result_node[0]~0 ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|result_node[0]~0 ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~0              ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~0              ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|result_node[0]~1 ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|result_node[0]~1 ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|result_node[0]   ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|result_node[0]   ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~1              ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~1              ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~2              ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~2              ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result36w~0    ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result36w~0    ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~3              ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~3              ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~4              ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~4              ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result36w~1    ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result36w~1    ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result36w      ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result36w      ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~5              ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~5              ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~6              ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~6              ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result37w~0    ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result37w~0    ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~7              ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~7              ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~8              ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~8              ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result37w~1    ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result37w~1    ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result37w      ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result37w      ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~9              ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~9              ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~10             ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~10             ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~11             ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~11             ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result44w~0    ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result44w~0    ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~12             ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~12             ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result44w~1    ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result44w~1    ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result44w      ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result44w      ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~13             ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~13             ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~14             ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~14             ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~15             ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~15             ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result65w~0    ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result65w~0    ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~16             ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|_~16             ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result65w~1    ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result65w~1    ; out0             ;
; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result65w      ; |ym4_1|lpm_mux:Mux9|mux_hfc:auto_generated|w_result65w      ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|result_node[0]~0 ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|result_node[0]~0 ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~0              ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~0              ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|result_node[0]~1 ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|result_node[0]~1 ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|result_node[0]   ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|result_node[0]   ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~1              ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~1              ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~2              ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~2              ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result36w~0    ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result36w~0    ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~3              ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~3              ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~4              ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~4              ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result36w~1    ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result36w~1    ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result36w      ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result36w      ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~5              ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~5              ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~6              ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~6              ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result37w~0    ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result37w~0    ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~7              ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~7              ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~8              ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~8              ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result37w~1    ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result37w~1    ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result37w      ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result37w      ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~9              ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~9              ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~10             ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~10             ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~11             ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~11             ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result44w~0    ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result44w~0    ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~12             ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~12             ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result44w~1    ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result44w~1    ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result44w      ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result44w      ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~13             ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~13             ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~14             ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~14             ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~15             ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~15             ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result65w~0    ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result65w~0    ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~16             ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|_~16             ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result65w~1    ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result65w~1    ; out0             ;
; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result65w      ; |ym4_1|lpm_mux:Mux8|mux_hfc:auto_generated|w_result65w      ; out0             ;
; |ym4_1|lpm_mux:Mux7|mux_1hc:auto_generated|_~0              ; |ym4_1|lpm_mux:Mux7|mux_1hc:auto_generated|_~0              ; out0             ;
; |ym4_1|lpm_mux:Mux7|mux_1hc:auto_generated|_~1              ; |ym4_1|lpm_mux:Mux7|mux_1hc:auto_generated|_~1              ; out0             ;
; |ym4_1|lpm_mux:Mux7|mux_1hc:auto_generated|result_node[0]~0 ; |ym4_1|lpm_mux:Mux7|mux_1hc:auto_generated|result_node[0]~0 ; out0             ;
; |ym4_1|lpm_mux:Mux7|mux_1hc:auto_generated|_~2              ; |ym4_1|lpm_mux:Mux7|mux_1hc:auto_generated|_~2              ; out0             ;
; |ym4_1|lpm_mux:Mux7|mux_1hc:auto_generated|_~3              ; |ym4_1|lpm_mux:Mux7|mux_1hc:auto_generated|_~3              ; out0             ;