ym4_1.tan.summary

7段数码是纯组合电路

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.481 ns
From           : ledin[0]
To             : ledout[5]$latch
From Clock     : --
To Clock       : ledin[1]
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.499 ns
From           : ledout[2]$latch
To             : ledout[2]
From Clock     : ledin[2]
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.360 ns
From           : ledin[3]
To             : ledout[0]$latch
From Clock     : --
To Clock       : ledin[2]
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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