ym4_1.vhd

7段数码是纯组合电路

library ieee;
use ieee.std_logic_1164.all;
entity ym4_1 is
port(ledin:in std_logic_vector(3 downto 0);
     ledout:out std_logic_vector(7 downto 0));
end entity ;architecture leds of ym4_1 is
begin
process(ledin)
begin 
case ledin is
when "0000"=>ledout<="00111111";
when "0001"=>ledout<="00000110";
when "0010"=>ledout<="01011001";
when "0011"=>ledout<="01001111";
when "0100"=>ledout<="01100110";
when "0101"=>ledout<="01101101";
when "0110"=>ledout<="01111101";
when "0111"=>ledout<="00000111";
when "1000"=>ledout<="01111111";
when "1001"=>ledout<="01111111";
when others=>null;
end case;
end process;
end;