decl7.vhd

来自「设计一个由甲、乙双方参赛」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decl7 IS 
  PORT( qin:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        led7s:out STD_LOGIC_VECTOR (6 DOWNTO 0));
END decl7;

ARCHITECTURE behav4 OF decl7 IS
BEGIN
  PROCESS (qin)
   begin
    case qin is
           WHEN "0001" => led7s<="0000110"; 
           WHEN "0010" => led7s<="1011011";
           WHEN "0011" => led7s<="1001111";
           WHEN "0100" => led7s<="1100110";
           WHEN "0101" => led7s<="1101101";
           WHEN "0110" => led7s<="1111101";
           WHEN "0111" => led7s<="0000111";
           WHEN "1000" => led7s<="1111111";
           WHEN "1001" => led7s<="1101111";
           WHEN OTHERS => led7s<="0111111";
       end case;
   end PROCESS;
end behav4;