selec.vhd

来自「设计一个由甲、乙双方参赛」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY selec IS 
  PORT( clk: IN STD_LOGIC;
        selo: out STD_LOGIC_VECTOR (1 DOWNTO 0));
END selec;

ARCHITECTURE behav1 OF selec IS
BEGIN
  PROCESS (clk)
     VARIABLE t:STD_LOGIC_VECTOR (1 DOWNTO 0);
  BEGIN
     if clk'event and clk='1' then 
        if    t="00" then t:="01";
        elsif t="01" then t:="10";
        elsif t="10" then t:="11";
        elsif t="11" then t:="00";
        end if;
      end if;
    selo<=t;
    end PROCESS;
END behav1;