📄 coma.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY coma IS
PORT( clk,aj,af,bj,bf,rd: IN STD_LOGIC;
sh: out STD_LOGIC_VECTOR (7 DOWNTO 0);
al,ah,bl,bh: out STD_LOGIC_VECTOR (3 DOWNTO 0));
END coma;
ARCHITECTURE behav2 OF coma IS
signal amark,bmark:integer;
BEGIN
k2:PROCESS (rd,clk,amark,bmark)
VARIABLE la,lb,ha,hb:STD_LOGIC_VECTOR (3 DOWNTO 0);
VARIABLE at,bt:integer;
BEGIN
if rd='0' or amark=21 or bmark=21 then
la:="0000";ha:="0000";at:=0;
lb:="0000";hb:="0000";bt:=0;
elsif clk'event and clk='1' then
if amark>at then
if la="1001" then
la:="0000";at:=at+1;ha:=ha+1;
else la:=la+1;at:=at+1;
end if;
elsif bmark>bt then
if lb="1001" then
lb:="0000";bt:=bt+1;hb:=hb+1;
else lb:=lb+1;bt:=bt+1;
end if;
end if;
end if;
al<=la;ah<=ha; bl<=lb;bh<=hb;
end PROCESS k2;
k1:PROCESS (rd,clk,amark,bmark)
VARIABLE sht:STD_LOGIC_VECTOR (7 DOWNTO 0);
VARIABLE a,b:STD_LOGIC;
BEGIN
if rd='0' or amark=21 or bmark=21 then
a:='0'; b:='0';sht:=(OTHERS=>'0');amark<=0;bmark<=0;
elsif clk'event and clk='1' then
if a='0' and b='0' and af='0' then
a:='1';sht:="10000000";
elsif a='0' and b='0' and bf='0' then
b:='1';sht:="00000001";
elsif a='0' and b='1' then
if sht<16 and sht/=0 then
if aj='0' then
bmark<=bmark+1;b:='0';sht:=(OTHERS=>'0');
else sht:=sht(6 DOWNTO 0)&'0';
end if;
elsif sht=0 then
bmark<=bmark+1;b:='0';
else
if aj='0' then
a:='1';b:='0';
else
sht:=sht(6 DOWNTO 0)&'0';
end if;
end if;
elsif a='1' and b='0' then
if sht>8 then
if bj='0' then
amark<=amark+1;a:='0';sht:=(OTHERS=>'0');
else sht:='0'&sht(7 DOWNTO 1);
end if;
elsif sht=0 then
amark<=amark+1;a:='0';
else
if bj='0' then
a:='0';b:='1';
else sht:='0'&sht(7 DOWNTO 1);
end if;
end if;
end if;
end if;
sh<=sht;
end PROCESS k1;
end behav2;
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