ch1f4.vhd

设计一个由甲、乙双方参赛

LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ch1f4 IS 
  PORT( sele: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
        c0,c1,c2,c3: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        qout:out STD_LOGIC_VECTOR (3 DOWNTO 0));
END ch1f4;

ARCHITECTURE behav3 OF ch1f4 IS
 BEGIN
 PROCESS (sele,c0,c1,c2,c3) 
 BEGIN
   CASE sele IS      
      WHEN "10"=>qout<=c2;   
      WHEN "11"=>qout<=c3;
      WHEN "01"=>qout<=c1;
      WHEN "00"=>qout<=c0; 
   END CASE;
 END PROCESS;
end behav3;