📄 frac_resampler_up_v2.mdl
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MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "resampler_up"
Location [6, 82, 1257, 949]
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ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "140"
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BlockType Inport
Name "data"
Position [130, 253, 160, 267]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "L"
Position [130, 468, 160, 482]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "phase"
Position [130, 518, 160, 532]
Port "3"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "valid_in"
Position [135, 658, 165, 672]
Port "4"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name " System Generator"
Tag "genX"
Ports []
Position [437, 763, 488, 813]
ShowName off
AttributesFormatString "System\\nGenerator"
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UserData "DataTag1"
SourceBlock "xbsIndex_r4/ System Generator"
SourceType "Xilinx System Generator Block"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
infoedit " System Generator"
xilinxfamily "Virtex2"
part "xc2v1000"
speed "-4"
package "bg575"
synthesis_tool "XST"
directory "./netlist"
testbench off
simulink_period "1"
sysclk_period "1.500000e+001"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "sysgen"
block_version "8.2.01"
sg_icon_stat "51,50,-1,-1,red,beige,0,07734"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
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" 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin"
" icon text');\nfprintf('','COMMENT: end icon text');\n"
sg_blockgui_xml "<!-- * Copyright (c) 2005, Xilinx, Inc. "
"All Rights Reserved. --><!-- * Reproduction or reuse, in any for"
"m, without the explicit written --><!-- * consent of Xilinx, Inc., is stri"
"ctly prohibited. --><sysgenblock has_userdata=\"true\" tag="
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"cs, gcbh);\" OpenFcn=\"xlSysgenGUI('startup',gcs,gcbh)\" ModelCloseFcn=\"xlSy"
"sgenGUI('Close',gcs,gcbh)\" PostSaveFcn=\"xlSysgenGUI('Save')\" />\n <librari"
"es>\n <library name=\"xbsIndex\" />\n <library name=\"xbsBasic\" />\n <lib"
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"erator_subsystem.mdl\" />\n <blockgui label=\"Xilinx System Generator\" >\n "
"<editbox evaluate=\"false\" multi_line=\"true\" name=\"infoedit\" read_only="
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"=\"xilinxfamily\" default=\"Virtex4\" label=\"Xilinx family\" />\n <editbox "
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"ditbox evaluate=\"false\" name=\"speed\" default=\"-10\" label=\"Speed\" />\n"
" <editbox evaluate=\"false\" name=\"package\" default=\"ff668\" label=\"Pack"
"age\" />\n <listbox evaluate=\"true\" name=\"synthesis_tool\" default=\"XST"
"\" label=\"Synthesis tool\" >\n <item value=\"Spectrum\" />\n <item value"
"=\"Synplify\" />\n <item value=\"Synplify Pro\" />\n <item value=\"XST\" "
"/>\n <item value=\"Precision\" />\n </listbox>\n <editbox evaluate=\"fals"
"e\" name=\"directory\" default=\"./netlist\" label=\"Target directory\" />\n "
" <checkbox evaluate=\"true\" name=\"testbench\" default=\"off\" label=\"Testb"
"ench\" />\n <editbox evaluate=\"true\" name=\"simulink_period\" default=\"1"
"\" label=\"Simulink period\" />\n <editbox evaluate=\"true\" name=\"sysclk_p"
"eriod\" default=\"10\" label=\"System clock period\" />\n <checkbox evaluate"
"=\"true\" name=\"incr_netlist\" default=\"off\" label=\"Incremental netlistin"
"g\" />\n <listbox evaluate=\"true\" name=\"trim_vbits\" default=\"Everywhere"
" in SubSystem\" label=\"Trim valid bits\" >\n <item value=\"According to Bl"
"ock Masks\" />\n <item value=\"Everywhere in SubSystem\" />\n <item value"
"=\"No Where in SubSystem\" />\n </listbox>\n <listbox evaluate=\"true\" nam"
"e=\"dbl_ovrd\" default=\"According to Block Masks\" label=\"Override with dou"
"bles\" >\n <item value=\"According to Block Masks\" />\n <item value=\"Ev"
"erywhere in SubSystem\" />\n <item value=\"No Where in SubSystem\" />\n </"
"listbox>\n <listbox evaluate=\"true\" name=\"core_generation\" default=\"Acc"
"ording to Block Masks\" label=\"Generate cores\" >\n <item value=\"Accordin"
"g to Block Masks\" />\n <item value=\"Everywhere Available\" />\n <item v"
"alue=\"Not Needed - Already Generated\" />\n </listbox>\n <checkbox evaluat"
"e=\"true\" name=\"run_coregen\" default=\"off\" label=\"Run CoreGen\" />\n <"
"checkbox evaluate=\"true\" name=\"deprecated_control\" default=\"off\" label="
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}
Block {
BlockType Reference
Name "L_value"
Ports [1, 1]
Position [185, 464, 240, 486]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type "
"Simulink integer, double and fixed point to Xilinx fixed point type.<P><P>Ha"
"rdware notes: In hardware these blocks become top level input ports."
arith_type "Unsigned"
n_bits "num_bits"
bin_pt "bin_pt-1"
quantization "Round (unbiased: +/- Inf)"
overflow "Saturate"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "20,20,356,423"
block_type "gatewayin"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
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" 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 65 65 0 ],[0 20 20 "
"0 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi"
"n icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In "
"','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','C"
"OMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Logical"
Ports [2, 1]
Position [1135, 572, 1180, 608]
SourceBlock "xbsIndex_r4/Logical"
SourceType "Xilinx Logical Block Block"
logical_function "AND"
inputs "2"
en off
latency "0"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
align_bp on
dbl_ovrd off
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "logical"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,36,2,1,white,blue,0,087b5522"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ')"
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" 32 26 18 10 4 12 4 4 7 4 4 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 36 3"
"6 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: "
"begin icon text ');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmo"
"de','on');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Register2"
Ports [2, 1]
Position [1040, 552, 1085, 603]
SourceBlock "xbsIndex_r4/Register"
SourceType "Xilinx Register Block"
init "0"
rst off
en on
dbl_ovrd off
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "register"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,51,2,1,white,blue,0,cc3303a0"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ')"
";\npatch([0 45 45 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22"
" 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[8 15 26 37 44 44 41 44 44 34"
" 44 37 26 15 8 18 8 8 11 8 8 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 51 "
"51 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT:"
" begin icon text ');\ncolor('black');port_label('input',1,'d');\ncolor('black"
"');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nc"
"olor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end "
"icon text');\n"
}
Block {
BlockType SubSystem
Name "addr_gen"
Ports [3, 2]
Position [590, 448, 675, 602]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "addr_gen"
Location [6, 82, 1274, 949]
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ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "delta"
Position [180, 333, 210, 347]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "phase"
Position [180, 573, 210, 587]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "ce"
Position [180, 513, 210, 527]
Port "3"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name "AddSub1"
Ports [3, 1]
Position [990, 307, 1040, 383]
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
use_carryout off
en on
latency "1"
precision "User Defined"
arith_type "Unsigned"
n_bits "num_bits-bin_pt"
bin_pt "0"
quantization "Truncate"
overflow "Wrap"
dbl_ovrd off
use_behavioral_HDL on
pipelined off
use_rpm on
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "addsub"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "50,76,3,1,white,blue,0,727db747"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s');\npatch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15"
" 30 34 38 54 41 29 20 34 20 29 41 54 38 34 30 15 ],[6 16 30 44 54 54 50 54 54"
" 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 60 60 0 ],[0 "
"58 58 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT"
": begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black"
"');port_label('input',2,'b');\ncolor('black');port_label('input',3,'en');\nco"
"lor('black');port_label('output',1,'\\bf{a + b}','texmode','on');\ncolor('bla"
"ck');disp('\\newline\\bf{}\\newlinez^{-1}','texmode','on');\nfprintf('','COMM"
"ENT: end icon text');\n"
}
Block {
BlockType Reference
Name "AddSub3"
Ports [2, 1]
Position [330, 285, 380, 360]
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
use_carryout off
en off
latency "0"
precision "User Defined"
arith_type "Unsigned"
n_bits "num_bits+1"
bin_pt "bin_pt"
quantization "Round (unbiased: +/- Inf)"
overflow "Wrap"
dbl_ovrd off
use_behavioral_HDL on
pipelined off
use_rpm on
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "addsub"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "50,75,2,1,white,blue,0,84d1e665"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s');\npatch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15"
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" 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 60 60 0 ],[0 "
"58 58 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT"
": begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black"
"');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a +"
" b}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Register"
Ports [2, 1]
Position [735, 293, 780, 342]
SourceBlock "xbsIndex_r4/Register"
SourceType "Xilinx Register Block"
init "0"
rst off
en on
dbl_ovrd off
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "register"
block_version "VER_STRING_GOES_HERE"
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