📄 frac_resampler_dn_v2.mdl
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en on
dbl_ovrd off
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "register"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,49,2,1,white,blue,0,cc3303a0"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s ');\npatch([0 45 45 0 ],[0 0 49 49 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 1"
"0 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[7 14 25 36 43 43 40 43 4"
"3 33 43 36 25 14 7 17 7 7 10 7 7 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0"
" 49 49 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMM"
"ENT: begin icon text ');\ncolor('black');port_label('input',1,'d');\ncolor('b"
"lack');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q')"
";\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: "
"end icon text');\n"
}
Block {
BlockType Reference
Name "Register1"
Ports [2, 1]
Position [740, 408, 785, 457]
SourceBlock "xbsIndex_r4/Register"
SourceType "Xilinx Register Block"
init "0"
rst off
en on
dbl_ovrd off
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "register"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,49,2,1,white,blue,0,cc3303a0"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s ');\npatch([0 45 45 0 ],[0 0 49 49 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 1"
"0 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[7 14 25 36 43 43 40 43 4"
"3 33 43 36 25 14 7 17 7 7 10 7 7 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0"
" 49 49 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMM"
"ENT: begin icon text ');\ncolor('black');port_label('input',1,'d');\ncolor('b"
"lack');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q')"
";\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: "
"end icon text');\n"
}
Block {
BlockType Reference
Name "Register2"
Ports [2, 1]
Position [990, 423, 1035, 472]
SourceBlock "xbsIndex_r4/Register"
SourceType "Xilinx Register Block"
init "0"
rst off
en on
dbl_ovrd off
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "register"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,49,2,1,white,blue,0,cc3303a0"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s ');\npatch([0 45 45 0 ],[0 0 49 49 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 1"
"0 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[7 14 25 36 43 43 40 43 4"
"3 33 43 36 25 14 7 17 7 7 10 7 7 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0"
" 49 49 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMM"
"ENT: begin icon text ');\ncolor('black');port_label('input',1,'d');\ncolor('b"
"lack');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q')"
";\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: "
"end icon text');\n"
}
Block {
BlockType Reference
Name "Reinterpret"
Ports [1, 1]
Position [645, 289, 685, 321]
SourceBlock "xbsIndex_r4/Reinterpret"
SourceType "Xilinx Type Reinterpreter Block"
infoedit "Changes type of samples without alterin"
"g their binary representation.<P><P>Hardware notes: In hardware this block co"
"sts nothing.<P><P>Example: Suppose the input is 6 bits wide, signed, with 2 "
"fractional bits, and the output is forced to unsigned with 0 fractional bits."
" Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output "
"of 56 (111000 in binary)."
force_arith_type on
arith_type "Unsigned"
force_bin_pt on
bin_pt "bin_pt"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "cast"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "40,32,1,1,white,blue,0,8982c1db"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 "
"16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 2"
"7 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 50 50 0 ],[0 3"
"2 32 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT:"
" begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT"
": end icon text');\n"
}
Block {
BlockType Scope
Name "Scope"
Ports [2]
Position [1230, 266, 1260, 299]
Floating off
Location [188, 390, 873, 903]
Open off
NumInputPorts "2"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "-5~-5"
YMax "5~5"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Reference
Name "Slice"
Ports [1, 1]
Position [570, 291, 615, 319]
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from eac"
"h input sample and presents it at the output. The output type is ordinarily "
"unsigned with binary point at zero, but can be Boolean when the slice is one "
"bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
nbits "num_bits"
boolean_output off
mode "Lower Bit Location + Width"
bit1 "1"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd off
has_advanced_control "0"
sggui_pos "20,20,449,389"
block_type "slice"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,28,1,1,white,blue,0,fe24a11e"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s ');\npatch([0 45 45 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([15 10 17 10"
" 15 22 24 26 34 28 22 18 26 18 22 28 34 26 24 22 15 ],[3 8 15 22 27 27 25 27 "
"27 21 27 23 15 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 2"
"8 28 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMEN"
"T: begin icon text ');\ncolor('black');port_label('output',1,'[a:b]');\nfprin"
"tf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Slice1"
Ports [1, 1]
Position [570, 406, 615, 434]
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from eac"
"h input sample and presents it at the output. The output type is ordinarily "
"unsigned with binary point at zero, but can be Boolean when the slice is one "
"bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
nbits "1"
boolean_output on
mode "Upper Bit Location + Width"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd off
has_advanced_control "0"
sggui_pos "20,20,449,389"
block_type "slice"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,28,1,1,white,blue,0,fe24a11e"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s ');\npatch([0 45 45 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([15 10 17 10"
" 15 22 24 26 34 28 22 18 26 18 22 28 34 26 24 22 15 ],[3 8 15 22 27 27 25 27 "
"27 21 27 23 15 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 2"
"8 28 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMEN"
"T: begin icon text ');\ncolor('black');port_label('output',1,'[a:b]');\nfprin"
"tf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Slice2"
Ports [1, 1]
Position [850, 306, 895, 334]
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from eac"
"h input sample and presents it at the output. The output type is ordinarily "
"unsigned with binary point at zero, but can be Boolean when the slice is one "
"bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
nbits "num_bits-bin_pt"
boolean_output off
mode "Upper Bit Location + Width"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd off
has_advanced_control "0"
sggui_pos "20,20,449,398"
block_type "slice"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,28,1,1,white,blue,0,fe24a11e"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s ');\npatch([0 45 45 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([15 10 17 10"
" 15 22 24 26 34 28 22 18 26 18 22 28 34 26 24 22 15 ],[3 8 15 22 27 27 25 27 "
"27 21 27 23 15 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 2"
"8 28 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMEN"
"T: begin icon text ');\ncolor('black');port_label('output',1,'[a:b]');\nfprin"
"tf('','COMMENT: end icon text');\n"
}
Block {
BlockType Outport
Name "addr"
Position [1275, 338, 1305, 352]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "clk_div"
Position [1275, 443, 1305, 457]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Register"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
Points [0, -125; -505, 0; 0, 110]
DstBlock "AddSub3"
DstPort 1
}
Branch {
DstBlock "Slice2"
DstPort 1
}
}
Line {
SrcBlock "delta"
SrcPort 1
Points [0, 0]
DstBlock "AddSub3"
DstPort 2
}
Line {
SrcBlock "ce"
SrcPort 1
Points [490, 0]
Branch {
Points [0, -75]
Branch {
Points [0, -115]
DstBlock "Register"
DstPort 2
}
Branch {
DstBlock "Register1"
DstPort 2
}
}
Branch {
Points [225, 0; 0, -60]
Branch {
Points [0, -90]
DstBlock "AddSub1"
DstPort 3
}
Branch {
DstBlock "Register2"
DstPort 2
}
}
}
Line {
SrcBlock "AddSub3"
SrcPort 1
Points [0, 0; 155, 0]
Branch {
Points [15, 0]
DstBlock "Slice"
DstPort 1
}
Branch {
Points [0, 95]
DstBlock "Slice1"
DstPort 1
}
}
Line {
SrcBlock "Slice"
SrcPort 1
DstBlock "Reinterpret"
DstPort 1
}
Line {
SrcBlock "Reinterpret"
SrcPort 1
DstBlock "Register"
DstPort 1
}
Line {
SrcBlock "Slice1"
SrcPort 1
DstBlock "Register1"
DstPort 1
}
Line {
SrcBlock "phase"
SrcPort 1
Points [700, 0; 0, -235]
DstBlock "AddSub1"
DstPort 2
}
Line {
SrcBlock "Register2"
SrcPort 1
Points [155, 0]
Branch {
DstBlock "clk_div"
DstPort 1
}
Branch {
Points [0, -160]
DstBlock "Scope"
DstPort 2
}
}
Line {
SrcBlock "Register1"
SrcPort 1
DstBlock "Register2"
DstPort 1
}
Line {
SrcBlock "Slice2"
SrcPort 1
DstBlock "AddSub1"
DstPort 1
}
Line {
SrcBlock "AddSub1"
SrcPort 1
Points [135, 0]
Branch {
DstBlock "addr"
DstPort 1
}
Branch {
Points [0, -70]
DstBlock "Scope"
DstPort 1
}
}
Annotation {
Name "Upcounter with Overflow"
Position [579, 81]
UseDisplayTextAsClickCallback off
}
Annotation {
Name "integer part"
Position [872, 288]
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