📄 frac_resampler_dn_v2.mdl
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System {
Name "frac_resampler_dn_v2"
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Ports []
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RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
infoedit " System Generator"
xilinxfamily "Virtex4"
part "xc4vsx25"
speed "-10"
package "ff668"
synthesis_tool "XST"
directory "./netlist_synplicity"
testbench off
simulink_period "1"
sysclk_period "10"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "sysgen"
block_version "8.2"
sg_icon_stat "51,50,-1,-1,red,beige,0,07734"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
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");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ico"
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sg_blockgui_xml "<!-- * Copyright (c) 2005, Xilinx, Inc. All "
"Rights Reserved. --><!-- * Reproduction or reuse, in any form, w"
"ithout the explicit written --><!-- * consent of Xilinx, Inc., is strictly"
" prohibited. --><sysgenblock has_userdata=\"true\" tag=\"gen"
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"cbh);\" OpenFcn=\"xlSysgenGUI('startup',gcs,gcbh)\" ModelCloseFcn=\"xlSysgenG"
"UI('Close',gcs,gcbh)\" PostSaveFcn=\"xlSysgenGUI('Save')\" />\n <libraries>\n"
" <library name=\"xbsIndex\" />\n <library name=\"xbsBasic\" />\n <library "
"name=\"xbsTools\" />\n </libraries>\n <subsystem_model file=\"system_generato"
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"inxfamily\" default=\"Virtex4\" label=\"Xilinx family\" />\n <editbox evalua"
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" evaluate=\"false\" name=\"speed\" default=\"-10\" label=\"Speed\" />\n <edi"
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