top_mt32.v

Master MemoryExamples for MT32 v1.0.0 Rtl core

//------------------------------------------------------------------------------
// 
// Name:                Master Memory 32 Example
// Module Name:         top_mt32
// Company:             Altera Corporation  www.altera.com 
// 
// Functional Description:
// 
//   This module is the top level of the Master 32-bit memory
//   example. The design example shows how to interface 
//   a 32-bit Master Function to a synchronous memory like altsyncram.
//   
//   This example also shows the sample master control logic required
//   to handle the case when the transaction is terminated by either a Target
//   Retry, Target Disconnect or Master Latency Timeout. If the
//   transaction is terminated before the entire data is transmitted,
//   the control logic will start a new PCI transaction and will
//   transfer the remaining data.
//   
//   This module instantiates the module mstr_mem32 the top level of
//   local design and the 32-bit PCI Master/Target core (pmt32)
//   
// Copyright:
//   Copyright 2004 Altera Corporation, All rights Reserved
//
//------------------------------------------------------------------------------
`timescale 1ns/1ns
module top_mt32 (/*AUTOARG*/
   // Outputs
   reqn, serrn, done, error, 
   // Inouts
   framen, irdyn, devseln, trdyn, stopn, ad, cben, par, 
   // Inputs
   clk, rstn, gntn, idsel, perrn, START, PCI_ADDR, LOCAL_ADDR, 
   LOCAL_DATA, CMD, XFR_LENGTH
   );

   input       clk;
   input       rstn;
   input       gntn;
   input       idsel;
   
   inout       framen;
   inout       irdyn;
   inout       devseln;
   inout       trdyn;
   inout       stopn;

   output      reqn;
   output      serrn;

   inout [31:0] ad;
   inout [3:0] 	cben;
   inout 	par;
   input 	perrn;

   // TB master control signals
   input 	START;
   input [31:0] PCI_ADDR;
   input [31:0] LOCAL_ADDR;
   input [31:0] LOCAL_DATA;
   input [3:0] 	CMD;
   input [10:0] XFR_LENGTH;
   output 	done;
   output 	error;
   
   // Internal Signals
   wire [31:0] 	l_adi, l_adro, l_dato;
   wire [3:0] 	l_cbeni, l_beno, l_cmdo;
   wire [9:0] 	lm_tsr;
   wire [11:0] 	lt_tsr;
   wire [6:0] 	cmd_reg;
   wire [6:0] 	stat_reg;
   wire [7:0] 	cache;
   
   pmt32 core (.clk(clk),
	       .rstn(rstn),
	       .gntn(gntn),
	       .idsel(idsel),
	       .l_adi(l_adi),
	       .l_cbeni(l_cbeni),
	       .lm_req32n(lm_req32n),
	       .lm_lastn(lm_lastn),
	       .lm_rdyn(lm_rdyn),
	       .lt_rdyn(lt_rdyn),
	       .lt_abortn(lt_abortn),
	       .lt_discn(lt_discn),
	       .lirqn(lirqn),
	       .framen(framen),
	       .irdyn(irdyn),
	       .devseln(devseln),
	       .trdyn(trdyn),
	       .stopn(stopn),
	       .intan(),
	       .reqn(reqn),
	       .serrn(serrn),
	       .l_adro(l_adro),
	       .l_dato(l_dato),
	       .l_beno(l_beno),
	       .l_cmdo(l_cmdo),
	       .lm_adr_ackn(lm_adr_ackn),
	       .lm_ackn(lm_ackn),
	       .lm_dxfrn(lm_dxfrn),
	       .lm_tsr(lm_tsr),
	       .lt_framen(lt_framen),
	       .lt_ackn(lt_ackn),
	       .lt_dxfrn(lt_dxfrn),
	       .lt_tsr(lt_tsr),
	       .cmd_reg(cmd_reg),
	       .stat_reg(stat_reg),
	       .cache(cache),
	       .ad(ad),
	       .cben(cben),
	       .par(par),
	       .perrn(perrn)
	       );


   mstr_mem32 be (.START_I			(START),
		  .PCI_ADDR_I			(PCI_ADDR[31:0]),
		  .LOCAL_ADDR_I			(LOCAL_ADDR[31:0]),
		  .LOCAL_DATA_I			(LOCAL_DATA[31:0]),
		  .PCI_CMD_I			(CMD[3:0]),
		  .XFR_LENGTH_I			(XFR_LENGTH[10:0]),
		  /*AUTOINST*/
		  // Outputs
		  .l_adi			(l_adi[31:0]),
		  .l_cbeni			(l_cbeni[3:0]),
		  .lm_req32n			(lm_req32n),
		  .lm_lastn			(lm_lastn),
		  .lm_rdyn			(lm_rdyn),
		  .lt_rdyn			(lt_rdyn),
		  .lt_abortn			(lt_abortn),
		  .lt_discn			(lt_discn),
		  .lirqn			(lirqn),
		  .done				(done),
		  .error			(error),
		  // Inputs
		  .clk				(clk),
		  .rstn				(rstn),
		  .l_adro			(l_adro[31:0]),
		  .l_dato			(l_dato[31:0]),
		  .l_beno			(l_beno[3:0]),
		  .l_cmdo			(l_cmdo[3:0]),
		  .lm_adr_ackn			(lm_adr_ackn),
		  .lm_ackn			(lm_ackn),
		  .lm_dxfrn			(lm_dxfrn),
		  .lm_tsr			(lm_tsr[9:0]),
		  .lt_framen			(lt_framen),
		  .lt_ackn			(lt_ackn),
		  .lt_dxfrn			(lt_dxfrn),
		  .lt_tsr			(lt_tsr[11:0]),
		  .cmd_reg			(cmd_reg[6:0]),
		  .stat_reg			(stat_reg[6:0]),
		  .cache			(cache[7:0])
		  );
   
	  
endmodule // top_mt32