readme

PCI vhdl for Fpga designer to design PCI IP

Revision date   December 1, 1994

Disclaimer:     These equations are for illustrative purposes only and are 
                included to illustrate the PCI controller design. The 
                equations have been simulated and are believed correct. 
                However, actual implementation will vary depending on the 
                design needs. Xilinx is not responsible for any conficts 
                that may exist between this design and the PCI Local Bus
                Specification. 
                
PCI_VHDL.ZIP:   VHDL source code for XC73144 Target Interface design in 
                applicatation note "Designing Flexible PCI Interfaces 
                with Xilinx EPLDs."

PCI_ABEL.ZIP    ABEL source code for XC73108 and XC7354 designs in 
                applicatation note "Designing Flexible PCI Interfaces 
                with Xilinx EPLDs."

                TARGET.ABL ABEL source code of UPDATED Target interface
                PARITY.ABL ABEL source code of UPDATED Target interface

PCI_V.ZIP       Verilog/HDL source code for XC3164 designs in 
                applicatation note "Fully Compliant PCI Interface in 
                XC3164A-2."

3100ACKL.ZIP    XC31OOA-2 PCI Component Electrical Checklist (WORD v6.0)
7300CKL.ZIP     XC730O-10 PCI Component Electrical Checklist (WORD v6.0)