vhdl基于实验开发板的按键处理与led显示.txt

VHDL基于实验开发板的按键处理与LED显示。

library ieee;
use ieee.std_logic_1164.all;
--实体
entity anjian is
port(clk:in std_logic;
     a:in std_logic_vector(5 downto 0);
     q:out std_logic_vector(16 downto 0));
end anjian;
--结构体
architecture mux of anjian is
--元件例化说明
component jcq is 
    port(data,clk,ld,load:in std_logic;
          qout:out std_logic);
end component;
component cfq is 
    port(data,clk,clr:in std_logic;
          qout:out std_logic);
end component;
--信号说明
signal clk1,clk2,clk3:std_logic;
signal b:std_logic_vector(5 downto 0);
signal e:std_logic_vector(5 downto 0);
signal c:std_logic_vector(15 downto 0);
signal d:std_logic_vector(16 downto 0):="00000000000000000";
begin
--第一分频
process(clk)
variable cnt:integer range 0 to 250000;
begin
if clk'event and clk='1' then cnt:=cnt+1;
if cnt<125000 then clk1<='0';
elsif cnt<250000 then clk1<='1';
else cnt:=0;clk1<='0';
end if;
end if;
end process;

process(clk1)
variable cnt1:integer range 0 to 100;
begin
if clk1'event and clk1='1' then cnt1:=cnt1+1;
if cnt1<50 then clk2<='0';
elsif cnt1<100 then clk2<='1';
else cnt1:=0; clk2<='0';
end if;
end if;
end process;
--按键消抖
process(clk1)
--variable t:integre range 0 to 50;
begin
b<=a;
end process;
--按钮数据存储

w124:for j in  0 to 5 generate
u2:cfq port map(b(j),b(j),b(1),e(j));
end generate w124;


--译码
process(b(0))
variable y:std_logic_vector(3 downto 0);
begin
y:=e(5)&e(4)&e(3)& e(2);
case y is
     when"0000"=>c<="0000000000000001";
     when"0001"=>c<="0000000000000011";
     when"0010"=>c<="0000000000000111";
     when"0011"=>c<="0000000000001111";
     when"0100"=>c<="0000000000011111";
     when"0101"=>c<="0000000000111111";
     when"0110"=>c<="0000000001111111";
     when"0111"=>c<="0000000011111111";
     when"1000"=>c<="0000000111111111";
     when"1001"=>c<="0000001111111111";
     when"1010"=>c<="0000011111111111";
     when"1011"=>c<="0000111111111111";
     when"1100"=>c<="0001111111111111";
     when"1101"=>c<="0011111111111111";
     when"1110"=>c<="0111111111111111";
     when"1111"=>c<="1111111111111111"; 
     when others=>c<="1111111111111111";
    
    end case;
end process;
--元件例化
d(0)<=d(16);
w123:for j in  0 to 15 generate
u1:jcq port map(d(j),clk2,c(j),b(0),d(j+1));
end generate w123;
process(clk2)
begin
if clk2'event and clk2='0' then q<=d;
end if;
end process;

end mux;

 

 

 

例化元件程序I:

library ieee;
use ieee.std_logic_1164.all;
entity cfq is
    port(data,clk,clr:in std_logic;
          qout:out std_logic);
end ;
architecture cf1 of cfq is
begin
process(clk,clr)
begin
if clr='1' then qout<='0';
elsif(clk'event and clk='1') then
qout<=data;
end if;
end process;
end cf1;

 

 

例化元件程序II

library ieee;
use ieee.std_logic_1164.all;
entity jcq is
    port(data,clk,ld,load:in std_logic;
          qout:out std_logic);
end ;
architecture cf of jcq is
begin
process(clk,load)
begin
if ( load='1')then
qout<=ld;
elsif(clk'event and clk='1') then
qout<=data;
end if;
end process;
end cf;