logic_unit.v

用verilog编写的4位ALU

`timescale 1ns/10ps

module logic_unit(
	logic_out,//Output, of Logic Unit, and is one of the inputs of mux_unit
	a,	//Input, 4-bit data input
	b,	//Input, 4-bit data input
	s1,	//Input, one of the two selecting signals to select the desired Logic Function 
	s0,	//Input, another selecting signal to select the desired Logic Function   
	rst_n);     //Input, synchoronous reset signal, effect LOW 

//Parameter declarations:
    parameter LOGIC_AND = 2'b00;
    parameter LOGIC_OR =2'b01;
    parameter LOGIC_XOR = 2'b10;
    parameter LOGIC_NXOR = 2'b11;
    	
//IO signals declarations:	
    output [3:0] logic_out;  
    input [3:0] a;
    input [3:0] b;
    input s1;
    input s0;
    input rst_n;
    
    reg [3:0] logic_out;  
    wire [3:0] a;
    wire [3:0] b;
    wire s1;
    wire s0;
    wire rst_n;
    
////Internal signals declarations:
    wire [1:0] logic_sel;    
    
    assign logic_sel={s1,s0};   	//Internal signal definition

//************** Main Logic Functions *********************    
    always@(s1 or s0 or a or b or rst_n)
    if(rst_n==1'b0)
    	logic_out <= 4'b0;
    else
    	case(logic_sel)//Select the Logic Function according to signals s1 and s0;
    	LOGIC_AND://00
    		logic_out <= a&b;
    	LOGIC_OR://01
    		logic_out <= a|b;
    	LOGIC_XOR://10
    		logic_out <= a^b;
    	LOGIC_NXOR://11
    		logic_out <= a~^b;
    	endcase 
    
endmodule