alu.v

用verilog编写的4位ALU

`timescale 1ns/10ps

module alu_top(
	alu_out,//Output, output of ALU, and is one of the inputs of mux_unit
	cout,
	a,	//Input, 4-bit data input
	b,	//Input, 4-bit data input
	m,	//Input, logic function or arithmetic function selector 
	s1,           //Input, one of the three selecting signals to select the desired Function
	s0,	//Input, one of the three selecting signals to select the desired Function
	c0,	//Input, one of the three selecting signals to select the desired Function   
	rst_n);	//Global reset signal, effect LOW
	
//IO signals declarations:	
    output [3:0] alu_out;  
    output cout;
    input [3:0] a;
    input [3:0] b;
    input m;
    input s1;
    input s0;
    input c0;
    input rst_n;
    
    wire [3:0] alu_out;  
    wire cout;
    wire [3:0] a;
    wire [3:0] b;
    wire m;
    wire s1;
    wire s0;
    wire c0;
    wire rst_n;

// Communication signals declarations  
    wire [3:0] logic_out;
    wire [3:0] arithmetic_out;
    
// Instantiate the three bottom units 
    logic_unit logic_func(
    	.logic_out(logic_out),
    	.a(a),
    	.b(b),
    	.s1(s1),
    	.s0(s0),
    	.rst_n(rst_n));
    arithmetic_unit arithmetic_func(
    	.arithmetic_out(arithmetic_out),
    	.cout(cout),
    	.a(a),
    	.b(b),
    	.s1(s1),
    	.s0(s0),
    	.c0(c0),
    	.rst_n(rst_n));
    mux_unit mux_func(
    	.mux_out(alu_out),
    	.logic_in(logic_out),
    	.arithmetic_in(arithmetic_out),
    	.m(m),
    	.rst_n(rst_n));
endmodule