arithmetic_unit.v

用verilog编写的4位ALU

`timescale 1ns/10ps  

module arithmetic_unit(
	arithmetic_out,//Output, output of Logic Unit, and is one of the inputs of mux_unit
	cout,
	a,	//Input, 4-bit data input
	b,	//Input, 4-bit data input
	s1,	//Input, one of the three selecting signals to select the desired Arithmetic Function 
	s0,           //Input, one of the three selecting signals to select the desired Arithmetic Function
	c0,	//Input, one of the three selecting signals to select the desired Arithmetic Function   
	rst_n);     //Input, synchoronous reset signal, effect LOW 
//Parameter declarations:
    parameter ARITHMETIC_FUNC1 = 3'b000;//Function: Transfer A; arithmetic_out=A
    parameter ARITHMETIC_FUNC2 = 3'b001;//Function: Increase A by 1; arithmetic_out=A+1
    parameter ARITHMETIC_FUNC3 = 3'b010;//Function: Add A and B; arithmetic_out=A+B
    parameter ARITHMETIC_FUNC4 = 3'b011;//Function: Increase the sum of A and B by 1; arithmetic_out=A+B+1
    parameter ARITHMETIC_FUNC5 = 3'b100;//Function: A plus one's compliment of B; arithmetic_out=A+B'
    parameter ARITHMETIC_FUNC6 = 3'b101;//Function: Subtract B from A(i.e. B'+A+1); arithmetic_out=A-B
    parameter ARITHMETIC_FUNC7 = 3'b110;//Function: B plus one's compliment of A; arithmetic_out=A'+B
    parameter ARITHMETIC_FUNC8 = 3'b111;//Function: B minus A(or A'+B+1); arithmetic_out=B-A;
	
//IO signals declarations:	
    output [3:0] arithmetic_out;  
    output cout;
    input [3:0] a;
    input [3:0] b;
    input s1;
    input s0;
    input c0;
    input rst_n;
    
    integer i;
    reg [3:0] sum1; 
    reg [3:0] arithmetic_out;  
    reg cout;
    
    wire [3:0] a;
    wire [3:0] b;
    wire s1;
    wire s0;
    wire c0;
    wire rst_n;
////Internal signals declarations:
    wire [2:0] arithmetic_sel;    
    
    assign arithmetic_sel={s1,s0,c0};   	//Internal signal definition

//************** Main Logic Functions *********************    
    always@(s1 or s0 or c0 or a or b or rst_n)
    if(rst_n==1'b0)
    	arithmetic_out <= 4'b0;
    else
    	case(arithmetic_sel)//Select the Logic Function according to signals s1 and s0;
    	ARITHMETIC_FUNC1://000:arithmetic_out = A
                arithmetic_out = a;
    	ARITHMETIC_FUNC2://001:arithmetic_out = A + 1  
    		begin
    		    arithmetic_out <= a + 1;
    		    if((a+1)>15) cout <= 1;
    		    else cout <= 0;
		    end
    	ARITHMETIC_FUNC3://010:arithmetic_out = A + B  	
    	 begin
    		    arithmetic_out <= a + b;
    		    if((a+b)>15) cout <= 1;
    		    else cout <= 0;
		    end
    	ARITHMETIC_FUNC4://011:arithmetic_out = A + B + 1
    		begin
    		    arithmetic_out <= a + b+1;
    		    if((a+b+1)>15) cout=1;
    		    else cout=0;
		    end
    	ARITHMETIC_FUNC5://100:arithmetic_out = A + B'
  		arithmetic_out <= a + ~b;
    	ARITHMETIC_FUNC6://101:arithmetic_out = A - B
    		arithmetic_out <= a - b;
    	ARITHMETIC_FUNC7://110:arithmetic_out = A' + B
  		arithmetic_out <= ~a + b;
    	ARITHMETIC_FUNC8://111:arithmetic_out = B - A
    		arithmetic_out <= b - a;
    	endcase 
  
endmodule