mux_unit.v

用verilog编写的4位ALU

`timescale 1ns/10ps
   
module mux_unit(
	mux_out,	//Output, output of the Unit, and is also the final output of ALU
	logic_in,	//Input, 4-bit data input
	arithmetic_in,//Input, 4-bit data input
	m,	//Input, the selecting signal to select the desired output   
	rst_n);     //Input, synchoronous reset signal, effect LOW 
//Parameter declarations:
    parameter LOGIC = 1'b0;//
    parameter ARITHMETIC = 1'b1;//
	
//IO signals declarations:	
    output [3:0] mux_out;  
    input [3:0] logic_in;
    input [3:0] arithmetic_in;
    input m;
    input rst_n;

    reg [3:0] mux_out;  
    wire [3:0] logic_in;
    wire [3:0] arithmetic_in;
    wire m;
    wire rst_n;
////Internal signals declarations:
    wire  output_sel;    
    
    assign output_sel=m;   	//Internal signal definition

//************** Main Logic Functions *********************    
    always@(m or logic_in or arithmetic_in or rst_n)
    if(rst_n==1'b0)
    	mux_out <= 4'b0;
    else
    	case(output_sel)//Select the Logic Function according to signals s1 and s0;
    	LOGIC://Select the Logic Unit output as the ALU ouput
    		mux_out <= logic_in ;
    	ARITHMETIC://Select the Arithmetic Unit output as the ALU ouput
    		mux_out <= arithmetic_in;
    	endcase 
    
endmodule