📄 __projnav.log
字号:
WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0023 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0024"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0024 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0025"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0025 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0026"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0026 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0027"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0027 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0028"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0028 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0029"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0029 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0030"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0030 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0031"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0031 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0032"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0032 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0033"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0033 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0034"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0034 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0035"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0035 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0036"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0036 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Mcompar__n0017_Mxor__n0037"...WARNING:LBEngine:353 - Module Mcompar__n0017_Mxor__n0037 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Annotating constraints to design from file "buzz1.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "buzz1.ngd" ...Writing NGDBUILD log file "buzz1.bld"...NGDBUILD done.Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.Done: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -tcl -command _cpldfit.tcl'
Creating TCL ProcessStarting: 'cpldfit -f _cpldfit.rsp buzz1.ngd'Release 4.1WP3.x - X9K/XPLA Optimizer/Partitioner E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Considering device XC95108-PC84.Flattening design.Tcl _cpldfit.tcl detected a return code of '-1' from program 'cpldfit -f _cpldfit.rsp buzz1.ngd'Done: failed with exit code: 0001.
ISE Auto-Make Log File-----------------------
Starting: 'jhdparse @_buzz1.jp'
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/Xilinx_WebPACK/data/simprim.lst
Scanning d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning buzz1.v
Writing buzz1.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
ISE Auto-Make Log File-----------------------
Updating: Fitter Report
Starting: 'exewrap @__buzz1_2prj_exewrap.rsp'
Creating TCL ProcessDone: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn buzz1.xst -ofn buzz1.syr'
Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn buzz1.xst -ofn buzz1.syr 'Release 4.1WP3.x - xst E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s --> =========================================================================---- Source ParametersInput Format : VERILOGInput File Name : buzz1.prj---- Target ParametersTarget Device : XC9500Output File Name : buzz1Output Format : NGCTarget Technology : 9500---- Source OptionsTop Module Name : buzz1Automatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Flip-Flop Type : DMux Extraction : YESResource Sharing : YESComplex Clock Enable Extraction : YES---- Target OptionsAdd IO Buffers : YESEquivalent register Removal : YESMacro Generator : AutoMACRO Preserve : YESXOR Preserve : YES---- General OptionsOptimization Criterion : SpeedOptimization Effort : 1Check Attribute Syntax : YESKeep Hierarchy : YES---- Other Optionswysiwyg : NO========================================================================= Compiling source file : buzz1.prjCompiling included source file 'buzz1.v'Module <buzz1> compiled.Continuing compilation of source file 'buzz1.prj'Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'Continuing compilation of source file 'buzz1.prj'No errors in compilationAnalysis of file <buzz1.prj> succeeded. Starting Verilog synthesis. Analyzing top module <buzz1>.Module <buzz1> is correct for synthesis.Synthesizing Unit <buzz1>. Related source file is buzz1.v. Found 20-bit comparator equal for signal <$n0017> created at line 13. Found 20-bit adder for signal <$old_counter_1>. Found 1-bit register for signal <buzzout_reg>. Found 20-bit register for signal <counter>. Summary: inferred 21 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s).Unit <buzz1> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 2 20-bit register : 1 1-bit register : 1# Adders/Subtractors : 1 20-bit adder : 1# Comparators : 1 20-bit comparator equal : 1=========================================================================Starting low level synthesis...Optimizing unit <buzz1> ...=========================================================================Final ResultsOutput File Name : buzz1Output Format : NGCOptimization Criterion : SpeedTarget Technology : 9500Keep Hierarchy : YESMacro Preserve : YESMacro Generation : AutoXOR Preserve : YESMacro Statistics# Xors : 39 1-bit xor2 : 39Design Statistics# Edif Instances : 390# I/Os : 18=========================================================================CPU : 4.01 / 4.23 s | Elapsed : 4.00 / 4.00 s --> EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.Done: completed successfully.
Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp buzz1 ngdbuild.rsp'
Creating TCL ProcessStarting: 'ngdbuild -f ngdbuild.rsp'Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc buzz1.ucf -p XC9500 buzz1.ngc buzz1.ngd Reading NGO file "F:/ /Xilinx/buzz/buzz1.ngc" ...Reading component libraries for design expansion...Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_10"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_10 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_11"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_11 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_12"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_12 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_13"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_13 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_14"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_14 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_15"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_15 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_16"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_16 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_17"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_17 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_18"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_18 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_19"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_19 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_4"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_4 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_5"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_5 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_6"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_6 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_7"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_7 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_8"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_8 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_counter_1_Mxor_Result_9"...WARNING:LBEngine:353 - Module Madd__old_counter_1_Mxor_Result_9 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running L⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -