buzz2.v

来自「利用xilinx实现一个简易的电子琴。简谱中的音名与频率一一对应。」· Verilog 代码 · 共 35 行

module buzz2 ( keyin,clk,buzzout,ledout);
	input clk;
	input [7:0] keyin;
	output buzzout;
	output [7:0] ledout;
	reg buzzout_reg;
	reg [30:0] counter;
	reg [7:0] keyin_reg;

	always @ (posedge clk)
	begin
		counter=counter+1;
	end

	always @ (keyin)
	begin
		keyin_reg=keyin;
		case(keyin_reg)
		8'b11111110:buzzout_reg=!counter[9];
		8'b11111101:buzzout_reg=!counter[10];
		8'b11111011:buzzout_reg=!counter[11];
		8'b11110111:buzzout_reg=!counter[12];
		8'b11101111:buzzout_reg=!counter[13];
		8'b11011111:buzzout_reg=!counter[14];
		8'b10111111:buzzout_reg=!counter[15];
		8'b01111111:buzzout_reg=!counter[16];
		default:buzzout_reg=1;
		endcase
	end

assign buzzout=buzzout_reg;
assign ledout=keyin_reg;
endmodule