📄 buzz2.rpt
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0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 25/11
Number of signals used by logic mapping into function block: 25
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 57 I/O I
counter_9 1 0 0 4 FB4_3 STD 58 I/O I
counter_8 1 0 0 4 FB4_4 STD (b) (b)
counter_7 1 0 0 4 FB4_5 STD 61 I/O I
counter_6 1 0 0 4 FB4_6 STD 62 I/O I
counter_5 1 0 0 4 FB4_7 STD (b) (b)
counter_4 1 0 0 4 FB4_8 STD 63 I/O I
counter_3 1 0 0 4 FB4_9 STD 65 I/O (b)
counter_2 1 0 0 4 FB4_10 STD (b) (b)
counter_16 1 0 0 4 FB4_11 STD 66 I/O (b)
counter_15 1 0 0 4 FB4_12 STD 67 I/O (b)
counter_14 1 0 \/2 2 FB4_13 STD (b) (b)
buzzout 8 3<- 0 0 FB4_14 STD 68 I/O O
counter_13 1 0 /\1 3 FB4_15 STD 69 I/O (b)
counter_12 1 0 0 4 FB4_16 STD (b) (b)
counter_11 1 0 0 4 FB4_17 STD 70 I/O (b)
counter_10 1 0 0 4 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "keyin<5>" 10: counter_1 18: counter_2.FBK.LFBK
2: "keyin<4>" 11: counter_10.FBK.LFBK
19: counter_3.FBK.LFBK
3: "keyin<7>" 12: counter_11.FBK.LFBK
20: counter_4.FBK.LFBK
4: "keyin<0>" 13: counter_12.FBK.LFBK
21: counter_5.FBK.LFBK
5: "keyin<6>" 14: counter_13.FBK.LFBK
22: counter_6.FBK.LFBK
6: "keyin<1>" 15: counter_14.FBK.LFBK
23: counter_7.FBK.LFBK
7: "keyin<2>" 16: counter_15.FBK.LFBK
24: counter_8.FBK.LFBK
8: "keyin<3>" 17: counter_16.FBK.LFBK
25: counter_9.FBK.LFBK
9: counter_0
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
counter_9 ........XX.......XXXXXXX................ 9 9
counter_8 ........XX.......XXXXXX................. 8 8
counter_7 ........XX.......XXXXX.................. 7 7
counter_6 ........XX.......XXXX................... 6 6
counter_5 ........XX.......XXX.................... 5 5
counter_4 ........XX.......XX..................... 4 4
counter_3 ........XX.......X...................... 3 3
counter_2 ........XX.............................. 2 2
counter_16 ........XXXXXXXX.XXXXXXXX............... 16 16
counter_15 ........XXXXXXX..XXXXXXXX............... 15 15
counter_14 ........XXXXXX...XXXXXXXX............... 14 14
buzzout XXXXXXXX..XXXXXXX.......X............... 16 16
counter_13 ........XXXXX....XXXXXXXX............... 13 13
counter_12 ........XXXX.....XXXXXXXX............... 12 12
counter_11 ........XXX......XXXXXXXX............... 11 11
counter_10 ........XX.......XXXXXXXX............... 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 8/28
Number of signals used by logic mapping into function block: 8
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB5_1 (b)
ledout<1> 1 0 0 4 FB5_2 STD 32 I/O O
ledout<2> 1 0 0 4 FB5_3 STD 33 I/O O
(unused) 0 0 0 5 FB5_4 (b)
ledout<3> 1 0 0 4 FB5_5 STD 34 I/O O
ledout<4> 1 0 0 4 FB5_6 STD 35 I/O O
(unused) 0 0 0 5 FB5_7 (b)
ledout<5> 1 0 0 4 FB5_8 STD 36 I/O O
ledout<6> 1 0 0 4 FB5_9 STD 37 I/O O
(unused) 0 0 0 5 FB5_10 (b)
ledout<7> 1 0 0 4 FB5_11 STD 39 I/O O
(unused) 0 0 0 5 FB5_12 40 I/O
(unused) 0 0 0 5 FB5_13 (b)
(unused) 0 0 0 5 FB5_14 41 I/O
(unused) 0 0 0 5 FB5_15 43 I/O
(unused) 0 0 0 5 FB5_16 (b)
counter_1 1 0 0 4 FB5_17 STD 44 I/O (b)
counter_0 1 0 0 4 FB5_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "keyin<5>" 4: "keyin<6>" 7: "keyin<3>"
2: "keyin<4>" 5: "keyin<1>" 8: counter_0.FBK.LFBK
3: "keyin<7>" 6: "keyin<2>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
ledout<1> ....X................................... 1 1
ledout<2> .....X.................................. 1 1
ledout<3> ......X................................. 1 1
ledout<4> .X...................................... 1 1
ledout<5> X....................................... 1 1
ledout<6> ...X.................................... 1 1
ledout<7> ..X..................................... 1 1
counter_1 .......X................................ 1 1
counter_0 .......X................................ 1 1
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
(unused) 0 0 0 5 FB6_2 45 I/O
(unused) 0 0 0 5 FB6_3 46 I/O
(unused) 0 0 0 5 FB6_4 (b)
(unused) 0 0 0 5 FB6_5 47 I/O
(unused) 0 0 0 5 FB6_6 48 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 50 I/O
(unused) 0 0 0 5 FB6_9 51 I/O
(unused) 0 0 0 5 FB6_10 (b)
(unused) 0 0 0 5 FB6_11 52 I/O
(unused) 0 0 0 5 FB6_12 53 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 54 I/O I
(unused) 0 0 0 5 FB6_15 55 I/O I
(unused) 0 0 0 5 FB6_16 (b)
(unused) 0 0 0 5 FB6_17 56 I/O I
(unused) 0 0 0 5 FB6_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"ledout<5>" = "keyin<5>"
"ledout<4>" = "keyin<4>"
"ledout<7>" = "keyin<7>"
"ledout<0>" = "keyin<0>"
"ledout<6>" = "keyin<6>"
"ledout<1>" = "keyin<1>"
"ledout<2>" = "keyin<2>"
"ledout<3>" = "keyin<3>"
/buzzout = "keyin<0>" * "keyin<1>" * "keyin<2>" *
"keyin<3>" * /"keyin<4>" * "keyin<5>" * "keyin<6>" *
"keyin<7>" * counter_13.FBK.LFBK
+ "keyin<0>" * "keyin<1>" * "keyin<2>" *
/"keyin<3>" * "keyin<4>" * "keyin<5>" * "keyin<6>" *
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